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Datasheet> All Categories > storage> storage> MT4C4001JDJ-6
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MT4C4001JDJ-6

Description
Fast Page DRAM, 1MX4, 60ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOJ-26/20
Categorystorage    storage   
File Size237KB，19 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT4C4001JDJ-6 Overview

Fast Page DRAM, 1MX4, 60ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOJ-26/20

MT4C4001JDJ-6 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeSOJ
package instruction0.300 INCH, PLASTIC, SOJ-26/20
Contacts20
Reach Compliance Codenot_compliant
ECCN codeEAR99
access modeFAST PAGE
Maximum access time60 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O typeCOMMON
JESD-30 codeR-PDSO-J20
JESD-609 codee0
length17.17 mm
memory density4194304 bit
Memory IC TypeFAST PAGE DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals20
word count1048576 words
character code1000000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ20/26,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)235
power supply5 V
Certification statusNot Qualified
refresh cycle1024
Maximum seat height3.61 mm
self refreshNO
Maximum standby current0.001 A
Maximum slew rate0.11 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width7.67 mm

MT4C4001JDJ-6 Preview

OBSOLETE
1 MEG x 4
FPM DRAM
DRAM
FEATURES
• 1,024-cycle refresh distributed across 16ms
(MT4C4001J) or 128ms (MT4C4001J L)
• Industry-standard pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +5V
±10%
power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-
RAS# (CBR), HIDDEN; optional Extended
• FAST PAGE MODE access cycle
MT4C4001J
PIN ASSIGNMENT (Top View)
20/26-Pin SOJ
(DA-1)
DQ1
DQ2
WE#
RAS#
A9
1
2
3
4
5
26
25
24
23
22
Vss
DQ4
DQ3
CAS#
OE#
20/26-Pin TSOP
(DB-1)
DQ1
DQ2
WE#
RAS#
A9
1
2
3
4
5
26
25
24
23
22
Vss
DQ4
DQ3
CAS#
OE#
OPTIONS
• Timing
60ns access
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
• Refresh Rate
Standard 16ms period
Extended 128ms period
MARKING
-6
DJ
TG
None
L
A0
A1
A2
A3
Vcc
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
A0
A1
A2
A3
Vcc
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
• Part Number Example: MT4C4001JDJ-6 L
KEY TIMING PARAMETERS
SPEED
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
Note:
The # symbol indicates signal is active LOW.
110ns
60ns
35ns
30ns
15ns
40ns
GENERAL DESCRIPTION
The MT4C4001J(L) is a randomly accessed, solid-state
memory containing 4,194,304 bits organized in a x4
configuration. RAS# is used to latch the first 10 bits and
CAS# the latter 10 bits. READ and WRITE cycles are se-
lected with the WE# input. A logic HIGH on WE# dictates
READ mode while a logic LOW on WE# dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of WE# or CAS#, whichever occurs last. If WE#
goes LOW prior to CAS# going LOW, the output pins
remain open (High-Z) until the next CAS# cycle.
If WE# goes LOW after data reaches the output pins, data-
out (Q) is activated and retains the selected cell data as long
as CAS# remains LOW (regardless of WE# or RAS#). This
late WE# pulse results in a READ WRITE cycle. The four
1 Meg x 4 FPM DRAM
D09.pm5 – Rev. 3/97
data inputs and four data outputs are routed through four
pins using common I/O, and pin direction is controlled by
WE# and OE#.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined page boundary. The FAST PAGE
MODE cycle is always initiated with a row address strobed-
in by RAS# followed by a column address strobed-in by
CAS#. CAS# may be toggled-in by holding RAS# LOW
and strobing-in different column addresses, thus executing
faster memory cycles. Returning RAS# HIGH terminates
the FAST PAGE MODE operation.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
OBSOLETE
1 MEG x 4
FPM DRAM
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE#
CAS#
*EARLY WRITE
DETECTION CIRCUIT
DATA-IN
BUFFER
4
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
4
4
DQ1
DQ2
DQ3
DQ4
OE#
COLUMN
ADDRESS
BUFFER(10)
REFRESH
CONTROLLER
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
10
COLUMN
DECODER
1024
4
SENSE AMPLIFIERS
I/O GATING
1024
REFRESH
COUNTER
COMPLEMENT
SELECT
10
ROW
ADDRESS
BUFFERS (10)
ROW SELECT
(1 of 1024)
ROW
DECODER
1024
1024
10
1024
1024 x 1024 x 4
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
Vcc
Vss
*NOTE:
1. If WE# goes LOW prior to CAS# going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If CAS# goes LOW prior to WE# going LOW, EW detection circuit output is a LOW (LATE WRITE).
1 Meg x 4 FPM DRAM
D09.pm5 – Rev. 3/97
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
OBSOLETE
1 MEG x 4
FPM DRAM
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY WRITE
READ WRITE
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
EARLY-WRITE
FAST-PAGE-MODE
READ-WRITE
RAS#-ONLY REFRESH
HIDDEN
REFRESH
CBR REFRESH
READ
WRITE
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
RAS#
H
L
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
H→L
CAS#
H→X
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H
L
L
L
WE#
X
H
L
H→L
H
H
L
L
H→L
H→L
X
H
L
H
OE#
X
L
X
L→H
L
L
X
X
L→H
L→H
X
L
X
X
t
R
t
C
DATA-IN/OUT
DQ1-DQ4
High-Z
Data-Out
Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out, Data-In
Data-Out, Data-In
High-Z
Data-Out
Data-In
High-Z
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
X
1 Meg x 4 FPM DRAM
D09.pm5 – Rev. 3/97
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
OBSOLETE
1 MEG x 4
FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to V
SS
.................... -1V to +7V
Operating Temperature, T
A
(ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6) (V
CC
= +5V
±10%)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
INPUT LEAKAGE CURRENT
Any input 0V
≤
V
IN
≤
V
CC
+1V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT (DQ is disabled; 0V
≤
V
OUT
≤
5.5V)
OUTPUT LEVELS
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
SYMBOL
V
CC
V
IH
V
IL
I
I
I
OZ
V
OH
V
OL
MIN
4.5
2.4
-1.0
-2
-10
2.4
0.4
MAX
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS# = CAS# = V
IH
)
STANDBY CURRENT: (CMOS)
(RAS# = CAS# = V
CC
-0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS#, CAS#, single address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT: RAS#-ONLY
Average power supply current
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended (L version only)
Average power supply current during Extended Refresh:
CAS# = 0.2V or CBR cycling; RAS# =
t
RAS (MIN); WE# = V
CC
-0.2V;
OE#, A0-A9 and D
IN
= V
CC
-0.2V or 0.2V; (D
IN
may be
left open);
t
RC = 125µs (1,024 rows at 125µs = 128ms)
SYMBOL
I
CC
1
I
CC
2
I
CC
2
(L only)
I
CC
3
-6
2
1
200
UNITS
mA
mA
µA
NOTES
MAX
5.5
V
CC
+1
0.8
2
10
UNITS
V
V
V
µA
µA
V
V
NOTES
110
mA
3, 26
I
CC
4
80
mA
3, 26
I
CC
5
110
mA
3, 26
I
CC
6
110
mA
3, 4
I
CC
7
(L only)
300
µA
3, 4,
24
1 Meg x 4 FPM DRAM
D09.pm5 – Rev. 3/97
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
OBSOLETE
1 MEG x 4
FPM DRAM
CAPACITANCE
PARAMETER
Input Capacitance: A0-A9
Input Capacitance: RAS#, CAS#, WE#, OE#
Input/Output Capacitance: DQ
SYMBOL
C
I
1
C
I
2
C
IO
MIN
MAX
5
7
7
UNITS
pF
pF
pF
NOTES
2
2
2
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 20) (V
CC
= +5V
±10%)
AC CHARACTERISTICS
PARAMETER
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column-address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# hold time (CBR REFRESH)
CAS# to output in Low-Z
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR REFRESH)
CAS# to WE# delay time
Write command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE# setup prior to RAS# during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
RAS# to CAS# delay time
Read command hold time (referenced to CAS#)
Read command setup time
-6
SYM
t
AA
t
AR
t
ASC
t
ASR
t
AWD
t
CAC
t
CAH
t
CAS
t
CHR
t
CLZ
t
CP
t
CPA
t
CRP
t
CSH
t
CSR
t
CWD
t
CWL
t
DH
t
DS
t
OD
t
OE
t
OEH
t
OFF
t
ORD
t
PC
t
PRWC
t
RAC
t
RAD
t
RAH
t
RAS
t
RASP
t
RC
t
RCD
t
RCH
t
RCS
MIN
45
0
0
55
15
10
15
10
0
10
10
60
10
40
15
10
0
3
15
3
0
35
85
15
10
60
60
110
20
0
0
10,000
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
18
4
13
35
4
18
19
19
23, 25
20
22
17, 25
15
15
15
60
10,000
100,000
16
1 Meg x 4 FPM DRAM
D09.pm5 – Rev. 3/97
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997,
Micron Technology, Inc.
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