CGS2535V Commercial Quad 1 to 4 Clock Drivers
CGS2535TV Industrial Quad 1 to 4 Clock Drivers
September 1995
CGS2535V
Commercial Quad 1 to 4 Clock Drivers
CGS2535TV
Industrial Quad 1 to 4 Clock Drivers
General Description
These Clock Generation and Support clock drivers are spe-
cifically designed for driving memory arrays requiring large
fanouts while operating at high speeds
This device meets the rise and fall time requirements of the
90 and 100 MHz Pentium
TM
processors
The CGS2535 is a non-inverting 4 to 16 driver with CMOS
I O structures The CGS2535 specification guarantees part-
to-part skew variation
Y
Y
Y
Y
Y
Y
Y
Y
Y
Features
Y
Y
650 ps part-to-part variation on positive or negative
transition
Operates with either 3 3V or 5 0V supply
Inputs 5V tolerant with V
CC
in 3 3V range
Symmetric output current drive 24 mA I
OH
I
OL
Industrial temperature range
b
40 C to
a
85 C
Symmetric package orientation
Large fanout for memory driving applications
Guaranteed 2 kV ESD protection
Implemented on National’s ABT family process
28-pin PLCC for optimum skew performance
Guaranteed
1 0 ns rise and fall times while driving 12 inches of
50X microstrip terminated with 25 pF
350 ps pin-to-pin skew (t
OSLH
and t
OSHL
)
Connection Diagrams
Pin Assignment for 28-Pin PLCC
TL F 11954 – 5
Truth Table
Input
In (0–3)
Output
ABCD Out (0–3)
CGS2535
Pentium
TM
is a trademark of Intel Corporation
C
1995 National Semiconductor Corporation
TL F 11954
TL F 11954 – 2
RRD-B30M105 Printed in U S A
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
7 0V
Input Voltage (V
I
)
Input Current
Current Applied to Output
(High Low)
Operating Temp Industrial grade
Comm grade
Storage Temperature Range
Airflow
0 LFM
225 LFM
500 LFM
900 LFM
7 0V
b
30 mA
Twice the Rated I
OH
I
OL
b
40 C to
a
85 C
0 C to
a
70 C
b
65 C to
a
150 C
Absolute Maximum Ratings
Recommended Operating
Conditions
Supply Voltage
V
CC
4 5V to 5 5V
V
CC
3 0V to 3 6V
Maximum Input Rise Fall Time (0 8V to 2 0V)
5 ns
Free Air Operating Temperature
Commercial
0 C to
a
70 C
b
40 C to
a
85 C
Industrial
Note
The Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed The device should not be operat-
ed at these limits The parametric values defined in the DC and AC Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings
The Recommended Operating Conditions will define the conditions for actu-
al device operation
Typical
i
JA
62 C W
43 C W
34 C W
27 C W
DC Electrical Characteristics
Over recommended operating free air temperature range All typical values are measured at V
CC
e
5V T
A
e
25 C
Symbol
V
IH
Parameter
Input High Level Voltage
Conditions
V
CC
(V)
30
45
55
V
IL
Input Low Level Voltage
30
45
55
V
IK
V
OH
Input Clamp Voltage
High Level Output Voltage
I
I
e b
18 mA
I
OH
e b
50
mA
45
30
45
55
I
OH
e b
24 mA
30
45
55
V
OL
Low Level Output Voltage
I
OL
e
50
mA
30
45
55
I
OL
e
24 mA
30
45
55
I
I
I
IH
I
IL
I
OLD
I
OHD
I
CC
C
IN
Input Current
Max Input Voltage
V
IH
e
7V
V
IH
e
V
CC
High Level Input Current
Low Level Input Current
Minimum Dynamic Output Current
Minimum Dynamic Output Current
Supply Current
Input Capacitance
V
IH
e
V
CC
V
IL
e
0V
V
OLD
e
1 65V (max)
V
OLD
e
0 9V (max)
V
OHD
e
3 85V (min)
V
OHD
e
2 1V (min)
55
36
55
55
55
30
55
30
36
55
50
5
b
5
Min
21
3 15
3 85
Typ
Max
Units
V
09
1 35
1 65
b
1 2
V
V
V
29
44
54
2 46
3 76
4 76
01
01
01
0 44
0 44
0 44
7
1
5
75
36
b
75
b
25
V
V
V
mA
mA
mA
mA
mA
75
235
mA
pF
Maximum test duration 2 0 ms one output loaded at a time
At V
CC
e
3 3V I
OLD
e
55 mA min
V
CC
e
3 6V I
OLD
e
64 mA min
V
CC
e
3 6V I
OHD
e b
66 mA min
At V
CC
e
3 3V I
OHD
e b
58 mA min
2
AC Electrical Characteristics
(Notes 1 2 and 3)
Over recommended operating free air temperature specified All typical values are measured at V
CC
e
5V T
A
e
25 C
CGS2535
Symbol
Parameter
V
CC
(V)
(Note 8)
T
A
e a
25 C
C
L
e
50 pF R
L
e
500X
Min
f
max
t
PLH
t
PHL
t
OSLH
t
OSHL
t
rise
t
fall
t
rise
t
fall
t
rise
t
fall
t
High
t
Low
t
PVLH
t
PVHL
Frequency Maximum
Low-to-High Propagation Delay
CK to O
n
High-to-Low Propagation Delay
CK to O
n
Maximum Skew Common Edge
Output-to-Output Variation (Notes 1 3)
Maximum Skew Common Edge
Output-to-Output Variation (Notes 1 3)
Rise Fall Time
(from 0 8V 2 0V to 2 0V 0 8V) (Note 5)
Rise Fall Time
(from 0 8V 2 0V to 2 0V 0 8V) (Note 6)
Rise Fall Time
(from 0 8V 2 0V to 2 0V 0 8V) (Note 7)
Pulse Width Duration High
(Notes 2 3)
Pulse Width Duration Low (Notes 2 3)
Part-to-Part Variation of
Low-to-High Transitions
Part-to-Part Variation of
High-to-Low Transitions
30
50
33
50
33
50
33
50
33
50
33
50
33
50
33
50
33
50
33
50
33
50
33
50
40
40
40
40
650
650
650
650
150
150
150
150
45
35
45
35
350
350
350
350
35
30
08
04
10
07
40
40
40
40
650
650
650
650
300
300
300
300
Typ
Max
T
A
e b
40 C to
a
85 C
(Note 4)
e
50 pF R
L
e
500X
C
L
Min
Typ
100
125
45
35
45
35
350
350
350
350
35
30
10
06
10
09
Max
MHz
ns
ns
ps
ps
ns
ns
ns
Units
ns
ps
Note 1
Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device The specifications apply to any outputs switching in the same direction either LOW to HIGH (t
OSLH
) or HIGH to LOW (t
OSHL
)
Note 2
Time high is measured with outputs at 2 0V or above Time low is measured with outputs at 0 8V or below Input waveform characteristics for t
High
t
Low
measurement f
e
66 67 MHz duty cycle
e
50%
Note 3
The input waveform has a rise and fall time transition time of 2 5 ns (10% to 90%)
Note 4
Industrial range (
b
40 C to
a
85 C) limits apply to the commercial temperature range (0 C to
a
70 C)
Note 5
These Rise and Fall times are measured with C
L
e
50 pF R
L
e
500X (see
Figure 1
)
Note 6
These Rise and Fall times are measured with C
L
e
25 pF R
L
e
500X (see
Figure 1
) and are guaranteed by design
Note 7
These Rise and Fall times are measured driving 12 inches of 50X microstrip terminated with equivalent C
L
e
25 pF (see
Figure 2
) and are guaranteed by
design
Note 8
Voltage Range 5 0 is 5 0V
g
0 5V 3 3 is 3 3V
g
0 3V
Note 9
For increased output drive output pins may be connected together when the corresponding input pins are connected together
3
Timing Information
TL F 11954 – 7
TL F 11954 –9
TL F 11954 – 10
FIGURE 1 A C Load (Reference Notes 5 6)
C
L
e
Total Load Including Probes
FIGURE 2 A C Load (Reference Note 7)
C
L
e
Total Load Including Probes
4
CGS2534 35 36 37
Memory Array Driving
In order to minimize the total load on the address bus quite
often memory arrays are driven by buffers while having the
inputs of the buffers tied together Although this practice
was feasible in the conventional memory designs in today’s
high speed large buswidth designs which require address
fetching at higher speeds this technique produces many
undesired results such as cross-talk and over undershoot
CGS2534 35 36 37 Quad 1 to 4 clock drivers were de-
signed specifically to address these application issues on
high speed large memory arrays systems
These drivers are optimized to drive large loads with 3 5 ns
propagation delays These drivers produce less noise while
reducing the total capacitive loading on the address bus by
having only four inputs tied together (see the diagram be-
low point A) This helps to minimize the overshoot and un-
dershoot by having only four outputs being switched simul-
taneously
Also this larger fan-out helps to save board space since for
every one of these drivers two conventional buffers were
typically being used
Another feature associated with these clock drivers is a
350 ps pin-to-pin skew specification The minimum skew
specification allows high speed memory system designers
to optimize the performance of their memory sub-system by
operating at higher frequencies without having concerns
about output-to-output (bank-to-bank) synchronization prob-
lems which are associated with driving high capacitive loads
(Point B)
The diagram below depicts a ‘‘2534 35 36 37’’ a memory
subsystem operating at high speed with large memory ca-
pacity The address bus is common to both the memory and
the CPU and I Os
These drivers can operate beyond 125 MHz and are also
available in 3V– 5V TTL CMOS versions with large current
drive
Device
2534
2535
2536
2537
V
CC
5
3 or 5
3 or 5
5
I O
TTL
CMOS
CMOS
TTL
Output Configuration
Inverting quad 1–4
Non-inverting quad 1–4
Inverting Non-inverting
d
2
Inverting quad 1–4 with series 8X output resistors
TL F 11954 – 8
5
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