HMA451S6AFR8N-UH datasheet, PDF

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HMA451S6AFR8N-UH: DescriptionDDR DRAM Module, 512MX64, CMOS, ROHS COMPLIANT, SODIMM-260; Categorystorage storage; File Size1MB，77 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HMA451S6AFR8N-UH Overview

DDR DRAM Module, 512MX64, CMOS, ROHS COMPLIANT, SODIMM-260

HMA451S6AFR8N-UH Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
package instruction	ROHS COMPLIANT, SODIMM-260
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Other features	AUTO/SELF REFRESH; WD-MAX
JESD-30 code	R-XDMA-N260
length	69.6 mm
memory density	34359738368 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	260
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512MX64
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
Maximum seat height	30.13 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.26 V
Minimum supply voltage (Vsup)	1.14 V
Nominal supply voltage (Vsup)	1.2 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	3.59 mm

HMA451S6AFR8N-UH Preview

260pin DDR4 SDRAM SODIMM

DDR4 SDRAM SO-DIMM

Based on 4Gb A-die

HMA425S6AFR6N

HMA451S6AFR8N

HMA451S7AFR8N

HMA41GS6AFR8N

HMA41GS7AFR8N

*SK hynix reserves the right to change products or specifications without notice.

Rev. 1.7 / Mar.2016

1

Revision History

Revision No.

0.1

0.2

0.21

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

History

Initial Release

Changed development plan

Module dimension Update (Detail-A : 0.125->1.125)

IDD Specification update

Changed maximum VDDSPD from 2.75V to 3.6

Revised CWL value

Corrected Pin Assignments

Added development plan (1Rx16)

Changed Module Dimension

Updated JEDEC Specification

Deleted Speed Grade Table

Updated IDD Specification(1Rx16)

Updated 2133Mbps (tCK(min) : 0.938ns->0.937ns)

Updated JEDEC Specification

Draft Date

Dec.2014

Jan.2015

Feb.2015

May.2015

Jun.2015

Jul.2015

Aug.2015

Oct.2015

Dec.2015

Mar.2016

Remark

Rev. 1.7 / Mar.2016

2

Description

SK hynix Unbuffered Small Outline DDR4 SDRAM DIMMs (Unbuffered Small Outine Double Data Rate Syn-

chronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules

that use DDR4 SDRAM devices. These DDR4 SDRAM Unbuffered Small Outline DIMMs are intended for use

as main memory when installed in systems such as micro servers and mobile personal computres.

Features

•

Power Supply: VDD=1.2V (1.14V to 1.26V)

VDDQ = 1.2V (1.14V to 1.26V)

VPP - 2.5V (2.375V to 2.75V)

VDDSPD=2.25V to 3.6V

Functionality and operations comply with the DDR4 SDRAM datasheet

16 internal banks

Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif-

ferent bank group accesses are available

Data transfer rates: PC4-2400,PC4-2133, PC4-1866, PC4-1600

Bi-Directional Differential Data Strobe

8 bit pre-fetch

Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)

Supports ECC error correction and detection

On-Die Termination (ODT)

Temperature sensor with integrated SPD

This product is in compliance with the RoHS directive.

Per DRAM Addressability is supported

Internal Vref DQ level generation is available

Ordering Information

Part Number

HMA425S6AFR6N-TF/UH

HMA451S6AFR8N-TF/UH

HMA451S7AFR8N-TF/UH

HMA41GS6AFR8N-TF/UH

HMA41GS7AFR8N-TF/UH

Density

2GB

4GB

8GB

Organization

256Mx64

512Mx64

512Mx72

1Gx64

1Gx72

Component Composition

256Mx16(H5AN4G6NAFR)*4

512Mx8(H5AN4G8NAFR)*8

512Mx8(H5AN4G8NAFR)*9

512Mx8(H5AN4G8NAFR)*16

512Mx8(H5AN4G8NAFR)*18

# of

ranks

1

2

Rev. 1.7 / Mar.2016

3

Key Parameters

MT/s

Grade

tCK

(ns)

1.25

1.071

0.937

0.833

CAS

Latency

(tCK)

11

13

15

17

tRCD

(ns)

tRP

(ns)

tRAS

(ns)

35

34

33

32

tRC

(ns)

48.75

(48.50)*

47.92

(47.50)*

47.06

(46.50)*

46.16

(45.75)*

CL-tRCD-tRP

DDR4-1600

DDR4-1866

DDR4-2133

DDR4-2400

-PB

-RD

-TF

-UH

13.75

(13.50)* (13.50)*

13.92

(13.50)* (13.50)*

14.06

(13.50)* (13.50)*

14.16

(13.75)*

14.16

(13.75)*

11-11-11

13-13-13

15-15-15

17-17-17

*SK hynix DRAM devices support optional downbinning to CL15, CL13 and CL11. SPD setting is programmed to match.

Address Table

2GB(1Rx16) 4GB(1Rx8) 8GB(2Rx8) 4GB(1Rx8) 8GB(2Rx8)

# of Bank Groups

Bank Address BG Address

Bank Address in a BG

Row Address

Column Address

Page size

4

BG0

BA0~BA1

A0~A14

A0~ A9

2 KB

4

BG0~BG1

BA0~BA1

A0~A14

A0~ A9

1 KB

4

BG0~BG1

BA0~BA1

A0~A14

A0~ A9

1 KB

4

BG0~BG1

BA0~BA1

A0~A14

A0~ A9

1 KB

4

BG0~BG1

BA0~BA1

A0~A14

A0~ A9

1 KB

Rev. 1.7 / Mar.2016

4

Pin Descriptions

Pin Name

A0-A16

BA0, BA1

BG0, BG1

RAS_n

1

CAS_n

2

WE_n

3

CS0_n, CS1_n,

CS2_n, CS3_n

CKE0, CEK1

ODT0, ODT1

ACT_n

DQ0-DQ63

CB0-CB7

DQS0_t-DQS8_t

DQS0_c-DQS8_c

DM0_n-DM8_n,

DBI0_n-DBI8_n

CK0_t, CK1_t

CK0_c, CK1_c

Description

SDRAM address bus

SDRAM bank select

SDRAM bank group select

SDRAM row address strobe

SDRAM column address strobe

SDRAM write enable

Rank Select Lines

SDRAM clock enable lines

SDRAM on-die termination control lines

SDRAM activate

DIMM memory data bus

DIMM ECC check bits

SDRAM data strobes

(positive line of differential pair)

SDRAM data strobes

(negative line of differential pair)

SDRAM data masks/data bus inversion

(x8-based x72 DIMMs)

SDRAM clocks (positive line of differen-

tial pair)

SDRAM clocks (negative line of differ-

ential pair)

RESET_n

EVENT_n

VTT

NC

Set SDRAMs to a Known State

SPD signals a thermal event has

occurred

Termination supply for the Address,

Command and Control bus

No connection

Pin Name

SCL

SDA

SA0-SA2

PARITY

VDD

VPP

C0, C1

VREFCA

VSS

VDDSPD

ALERT_n

Description

I

2

C serial bus clock for SPD/TS

I

2

C serial bus data line for SPD/TS

I

2

C slave address select for SPD/TS

SDRAM parity input

SDRAM I/O & core power supply

SDRAM activating power supply

Chip ID lines for 3DS components

SDRAM command/address reference

supply

Power supply return (ground)

Serial SPD/TS positive power supply

SDRAM ALERT_n

1. RAS_n is a multiplexed function with A16.

2. CAS_n is a multiplexed function with A15.

3. WE_n is a multiplexed function with A14.

Rev. 1.7 / Mar.2016

5

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HMA451S6AFR8N-UH Related Products

	HMA451S6AFR8N-UH	HMA451S6AFR8N-TF	HMA451S7AFR8N-TF	HMA451S7AFR8N-UH
Description	DDR DRAM Module, 512MX64, CMOS, ROHS COMPLIANT, SODIMM-260	DDR DRAM Module, 512MX64, CMOS, ROHS COMPLIANT, SODIMM-260	DDR DRAM Module, 512MX72, CMOS, ROHS COMPLIANT, SODIMM-260	DDR DRAM Module, 512MX72, CMOS, ROHS COMPLIANT, SODIMM-260
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	SK Hynix	SK Hynix	SK Hynix	SK Hynix
package instruction	ROHS COMPLIANT, SODIMM-260	ROHS COMPLIANT, SODIMM-260	DIMM,	DIMM,
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
Other features	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX
JESD-30 code	R-XDMA-N260	R-XDMA-N260	R-XDMA-N260	R-XDMA-N260
length	69.6 mm	69.6 mm	69.6 mm	69.6 mm
memory density	34359738368 bit	34359738368 bit	38654705664 bit	38654705664 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	64	72	72
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	260	260	260	260
word count	536870912 words	536870912 words	536870912 words	536870912 words
character code	512000000	512000000	512000000	512000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
organize	512MX64	512MX64	512MX72	512MX72
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260	260	260	260
Maximum seat height	30.13 mm	30.13 mm	30.13 mm	30.13 mm
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.26 V	1.26 V	1.26 V	1.26 V
Minimum supply voltage (Vsup)	1.14 V	1.14 V	1.14 V	1.14 V
Nominal supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	20	20	20	20
width	3.59 mm	3.59 mm	3.59 mm	3.59 mm

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