IDT54FCT162952BTE datasheet, PDF

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IDT54FCT162952BTE: DescriptionRegistered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56; Categorylogic logic; File Size75KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT54FCT162952BTE Overview

Registered Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56

IDT54FCT162952BTE Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
Parts packaging code	DFP
package instruction	DFP,
Contacts	56
Reach Compliance Code	unknown
Other features	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; CLOCK ENABLE; MAX OUTPUT SKEW = 0.5NS
series	FCT
JESD-30 code	R-GDFP-F56
JESD-609 code	e0
length	18.415 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	56
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE WITH SERIES RESISTOR
Output polarity	TRUE
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
propagation delay (tpd)	8 ns
Certification status	Not Qualified
Maximum seat height	2.413 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	0.635 mm
Terminal location	DUAL
width	9.652 mm

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16-BIT TRI-PORT

BUS EXCHANGER

Integrated Device Technology, Inc.

IDT73720/A

FEATURES:

• High-speed 16-bit bus exchange for interbus communica-

tion in the following environments:

— Multi-way interleaving memory

— Multiplexed address and data busses

• Direct interface to R3051 family RISChipSet™

— R3051™ family of integrated RISController™ CPUs

— R3721 DRAM controller

• Data path for read and write operations

• Low noise 12mA TTL level outputs

• Bidirectional 3-bus architecture: X, Y, Z

— One CPU bus: X

— Two (interleaved or banked) memory busses:Y & Z

— Each bus can be independently latched

• Byte control on all three busses

• Source terminated outputs for low noise and undershoot

control

• 68-pin PLCC and 80-pin PQFP package

• High-performance CMOS technology.

DESCRIPTION:

The IDT73720/A Bus Exchanger is a high speed 16-bit bus

exchange device intended for inter-bus communication in

interleaved memory systems and high performance multi-

plexed address and data busses.

The Bus Exchanger is responsible for interfacing between

the CPU A/D bus (CPU address/data bus) and multiple

memory data busses.

The 73720/A uses a three bus architecture (X, Y, Z), with

control signals suitable for simple transfer between the CPU

bus (X) and either memory bus (Y or Z). The Bus Exchanger

features independent read and write latches for each memory

bus, thus supporting a variety of memory strategies. All three

ports support byte enable to independently enable upper and

lower bytes.

FUNCTIONAL BLOCK DIAGRAM

OEYL

LEXY

Y-WRITE

LATCH

LEYX

OEXL

0:7

8:15

OEXU

16 X

OEXU

OEXL

OEYU

OEYL

OEZU

OEZL

Z-READ

LATCH

Z-WRITE

LATCH

OEZU

NOTE:

1. Logic equations for bus control:

OEXU = T/

* .

OEU

*; OEXL = T/

* .

OEL

*; OEYU = T/

. PATH .

OEU

OEYL = T/

. PATH .

OEL

*; OEZU = T/

. PATH* .

OEU

*; OEZL = T/

. PATH* .

Figure 1. 73720 Block Diagram

0:7

8:15

(Even Path)

Y-READ

LATCH

OEYU

PATH

BUS CONTROL

T/R

OEU

OEL

LEZX

OEZL

0:7

8:15

(Odd Path)

2527 drw 01

LEXZ

OEL

RISChipSet, RISController, R305x, R3051, R3052 are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

Integrated Device Technology, Inc.

AUGUST 1995

11.5

DSC-2046/6

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