W27E02Q-90 datasheet, PDF - EEWORLD Datasheet

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W27E02Q-90: DescriptionEEPROM, 256KX8, 90ns, Parallel, CMOS, PDSO32, 8 X 14 MM, STSOP-32; Categorystorage storage; File Size277KB，16 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W27E02Q-90 Overview

EEPROM, 256KX8, 90ns, Parallel, CMOS, PDSO32, 8 X 14 MM, STSOP-32

W27E02Q-90 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Winbond Electronics Corporation
Parts packaging code	TSOP
package instruction	TSOP1, TSSOP32,.56,20
Contacts	32
Reach Compliance Code	unknown
ECCN code	3A991.B.1.B.1
Maximum access time	90 ns
command user interface	NO
Data polling	NO
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	12.4 mm
memory density	2097152 bit
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	32
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP32,.56,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.0001 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	NO
width	8 mm

W27E02Q-90 Preview

Preliminary W27E02

256K

8 ELECTRICALLY ERASABLE EPROM

1. GENERAL DESCRIPTION

The W27E02 is a high speed, low power consumption Electrically Erasable and Programmable Read

Only Memory organized as 262,144

8 bits. It requires only one supply in the range of 5.0V

10% in

normal read mode. The W27E02 provides an electrical chip erase function.

2. FEATURES

•

Single power supply voltage: 5.0V

±10%

High speed access time: 70/90 nS (max.)

Read operating current: 30 mA (max.)

Erase/Programming operating current:

30 mA (max.)

Standby current: 20

µA

(max.)

+12V erase/programming voltage

•

Fully static operation

•

All inputs and outputs directly TTL/CMOS

compatible

•

Three-state outputs

•

Available packages: 32-pin 600 mil DIP, 32-lead

PLCC and 32-lead STSOP

3. PIN CONFIGURATIONS

4. BLOCK DIAGRAM

Vss

Vpp

A16

A15

A12

Vss

32-pin

PDIP

#PGM

A17

A14

A13

A11

#OE

A10

#CE

12 1

13 4

3 2

A A A

1 1 1

2 5 6

V P A

D G 1

D M

0 29

2 22

0 21

#PGM

#CE

#OE

CONTROL

OUTPUT

BUFFER

32-lead PLCC

1 1

7 8

A14

A13

A11

#OE

A10

#CE

A17

DECODER

CORE

ARRAY

Q Q V Q Q Q Q

1 2 s 3 4 5 6

5. PIN DESCRIPTION

A11

A13

A14

A17

#PGM

A16

A15

A12

32-lead STSOP

#OE

A10

#CE

V SS

SYMBOL

−

A17

−

#CE

#OE

#PGM

Vss

DESCRIPTION

Address Inputs

Data Inputs/Outputs

Chip Enable

Output Enable

Program Enable

Program/Erase Supply Voltage

Power Supply

Ground

No Connection

-1-

Publication Release Date: May 30, 2002

Revision A1

Preliminary W27E02

6. FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27E02 has two control functions and both of these produce data at

the outputs.

#CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins.

When addresses are stable, the address access time (T

ACC

) is equal to the delay from #CE to output

), and data are available at the outputs T

after the falling edge of #OE, if T

ACC

and T

timings

are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,

which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an

hour), the W27E02 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an

EPROM writer with a special erase algorithm.

There are two ways to enter Erase mode. One is to raise V

to V

(12V), V

= V

(5.0V ), #CE low,

#OE high, A9 = V

(12V), and all other address pins are kept at fixed low or high. Pulsing #PGM low

starts the erase operation. The other way is somewhat like flash, by programming two consecutive

commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex)

to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the #PGM pulse

widths of these two commands are different: One is 100

µS,

while the other is 100 mS. Please refer to

the Smart Erase Algorithm 1 & 2.

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been

successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase

margin. This mode will be entered after the erase operation if V

= V

(5.0V ), #CE low, and #OE low,

#PGM high

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only

way to change cell data from "1" to "0." The program mode is entered when V

is raised to V

(12V),

= V

(5.0V ), #CE low, #OE high, the address pins equal the desired addresses, and the input pins

equal the desired inputs. Pulsing #PGM low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully programmed

with the desired data or not. Hence, after each byte is programmed, a program verify operation should

be performed. The program verify mode automatically ensures a substantial program margin. This mode

will be entered after the program operation if V

= V

(12V), #CE low, #OE low

and #PGM high.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different

data. When #CE high, erasing or programming of non-target chips is inhibited, so that except for the

#CE, the W27E02 may have common inputs.

-2-

Preliminary W27E02

Standby Mode

The standby mode significantly reduces V

current. This mode is entered when #CE high. In standby

mode, all outputs are in a high impedance state, independent of #OE and #PGM.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E02 provides two control inputs for

multiple memory connections. Two-line control provides for lowest possible memory power dissipation

and ensures that data bus contention will not occur.

System Considerations

EPROM power switching characteristics require careful device decoupling. System designers are

concerned with three supply current issues: standby current levels (I

), active current levels (I

), and

transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes

depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling

capacitor selection will suppress transient voltage peaks. Each device should have a 0.1

µF

ceramic

capacitor connected between its V

and Vss. This high frequency, low inherent-inductance capacitor

should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7

µF

electrolytic capacitor should be placed at the array's power supply connection between V

and Vss.

The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

7. TABLE OF OPERATING MODES

= 5.0V

±10

%, Vpp = Vp

= V

= 12V, V

= V

= 5.0V, X = V

or V

PINS

MODE

#CE

#OE

#PGM

OTER

ADDR

OUTPUTS

Read

Output Disable

Standby (TTL)

Standby (CMOS)

Program

Program Verify

Program Inhibit

Erase1

Erase2

Erase Verify

Erase Inhibit

Product Identifier -

Manufacturer

Product Identifier -

Device

±0.3V

OUT

High Z

OUT

High Z

FF (Hex)

AA (Hex)

10 (Hex)

OUT

High Z

DA (Hex)

85 (Hex)

First command:

Addr. = 5555 (hex)

Second command:

Addr. = 2AAA (hex)

-3-

Publication Release Date: May 30, 2002

Revision A1

Preliminary W27E02

8. DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

Operation Temperature

Storage Temperature

Voltage on all Pins with Respect to Ground Except V

DD,

and A9 Pins

Voltage on V

Pin with Respect to Ground

Voltage on V

Pin with Respect to Ground

Voltage on A9 Pin with Respect to Ground

RATING

0 to +70

-65 to +125

-0.5 to V

+0.5

-0.5 to +7.0

-0.5 to +14.5

UNIT

°C

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

9. CAPACITANCE

= 5.0V

±10%,

= 25° C, f = 1 MHz)

PARAMETER

Input Capacitance

Output Capacitance

SYMBOL

OUT

CONDITIONS

= 0V

OUT

= 0V

MAX.

UNIT

10. READ OPERATION DC CHARACTERISTICS

= 5.0V

±10%,

= 0 to 70° C)

PARAMETER

Input Load Current

Output Leakage

Current

Standby V

Current

(TTL input)

Standby V

Current

(CMOS input)

Operating Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Operating Voltage

SYM.

CONDITIONS

= 0V to V

OUT

= 0V to V

#CE = V

±0.2V

#CE = V

IL,

OUT

= 0 mA,

f = 5 MHz

= V

= 1.6 mA

= -0.1 mA

LIMITS

MIN.

-5

-10

-0.3

2.0

2.4

DD -

0.7

TYP.

MAX.

100

0.8

+0.5

0.4

UNIT

µA

-4-

Preliminary W27E02

Program/Erase DC Characteristics

= 25° C, V

= 5.0V

±10

%, V

= 12V)

PARAMETER

Input Load Current

Program Current

Erase Current

Program Current

Erase Current

Input Low Voltage

Input High Voltage

Output Low Voltage (Verify)

Output High Voltage (Verify)

A9 Silicon I.D. Voltage

A9 Erase Voltage

Program Voltage

Erase Voltage

Supply Voltage

(Program)

Supply Voltage (Erase)

Supply Voltage (Erase

Verify)

SYM.

CONDITIONS

MIN.

= V

or V

#CE = V

IL,

#OE = V

IH,

#PGM = V

#CE = V

IL,

#OE = V

IH,

#PGM = V

, A9 = V

#CE = V

IL,

#OE = V

IH,

#PGM = V

#CE = V

IL,

#OE = V

IH,

#PGM = V

, A9 = V

= 2.1 mA

= -0.4 mA

-10

-0.3

2.4

11.5

11.75

4.5

LIMITS

TYP.

12.0

5.0

MAX.

0.8

5.5

0.45

12.5

14.25

12.25

14.25

5.5

UNIT

µA

Note: V

must be applied simultaneously or before V

and removed simultaneously or after V

-5-

Publication Release Date: May 30, 2002

Revision A1

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Description	EEPROM, 256KX8, 90ns, Parallel, CMOS, PDSO32, 8 X 14 MM, STSOP-32	EEPROM, 256KX8, 70ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32	EEPROM, 256KX8, 70ns, Parallel, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32	EEPROM, 256KX8, 90ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32	EEPROM, 256KX8, 70ns, Parallel, CMOS, PDSO32, 8 X 14 MM, STSOP-32	EEPROM, 256KX8, 90ns, Parallel, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation
Parts packaging code	TSOP	QFJ	DIP	QFJ	TSOP	DIP
package instruction	TSOP1, TSSOP32,.56,20	PLASTIC, LCC-32	DIP, DIP32,.6	QCCJ, LDCC32,.5X.6	TSOP1, TSSOP32,.56,20	DIP, DIP32,.6
Contacts	32	32	32	32	32	32
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A991.B.1.B.1	3A991.B.1.B.1	3A991.B.1.B.1	3A991.B.1.B.1	3A991.B.1.B.1	3A991.B.1.B.1
Maximum access time	90 ns	70 ns	70 ns	90 ns	70 ns	90 ns
command user interface	NO	NO	NO	NO	NO	NO
Data polling	NO	NO	NO	NO	NO	NO
JESD-30 code	R-PDSO-G32	R-PQCC-J32	R-PDIP-T32	R-PQCC-J32	R-PDSO-G32	R-PDIP-T32
JESD-609 code	e0	e0	e0	e0	e0	e0
length	12.4 mm	13.97 mm	41.91 mm	13.97 mm	12.4 mm	41.91 mm
memory density	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit
Memory IC Type	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM	EEPROM
memory width	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1
Number of terminals	32	32	32	32	32	32
word count	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000	256000	256000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	256KX8	256KX8	256KX8	256KX8	256KX8	256KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP1	QCCJ	DIP	QCCJ	TSOP1	DIP
Encapsulate equivalent code	TSSOP32,.56,20	LDCC32,.5X.6	DIP32,.6	LDCC32,.5X.6	TSSOP32,.56,20	DIP32,.6
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	CHIP CARRIER	IN-LINE	CHIP CARRIER	SMALL OUTLINE, THIN PROFILE	IN-LINE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	225	NOT SPECIFIED	225	240	NOT SPECIFIED
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Programming voltage	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	3.56 mm	5.33 mm	3.56 mm	1.2 mm	5.33 mm
Maximum standby current	0.0001 A	0.0001 A	0.0001 A	0.0001 A	0.0001 A	0.0001 A
Maximum slew rate	0.03 mA	0.03 mA	0.03 mA	0.03 mA	0.03 mA	0.03 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	NO	YES	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
Terminal form	GULL WING	J BEND	THROUGH-HOLE	J BEND	GULL WING	THROUGH-HOLE
Terminal pitch	0.5 mm	1.27 mm	2.54 mm	1.27 mm	0.5 mm	2.54 mm
Terminal location	DUAL	QUAD	DUAL	QUAD	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	NOT SPECIFIED	30	30	NOT SPECIFIED
switch bit	NO	NO	NO	NO	NO	NO
width	8 mm	11.43 mm	15.24 mm	11.43 mm	8 mm	15.24 mm

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