5V41234NLGI datasheet, PDF - EEWORLD Datasheet

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5V41234NLGI: DescriptionVFQFPN-16, Tube; CategoryThe embedded processor and controller Microcontrollers and processors; File Size322KB，14 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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5V41234NLGI Overview

VFQFPN-16, Tube

5V41234NLGI Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	HVQCCN, LCC16,.12SQ,20
Contacts	16
Manufacturer packaging code	NLG16P2
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	VFQFN- N 3 X 3 X 1.0 MM - NO LEAD
JESD-30 code	S-XQCC-N16
JESD-609 code	e3
length	3 mm
Humidity sensitivity level	3
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	100 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC16,.12SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Master clock/crystal nominal frequency	25 MHz
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum slew rate	70 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

5V41234NLGI Preview

DATASHEET

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Typical Applications

One output synthesizer for PCIe Gen1/2/3

5V41234

Features

•

3 x 3 mm 16-QFN package; very small board footprint

•

Spread-spectrum capable; reduces EMI

•

Outputs can be terminated to LVDS; can drive a wider

variety of devices

Description

The 5V41234 is a PCIe Gen2/3 compliant spread spectrum

capable clock generator. The device has 1 differential

HCSL output and can be used in communication or

embedded systems to substantially reduce

electro-magnetic interference (EMI). Spread spectrum can

be enabled via a select pin.

•

Spread enable via pin selection; no software required to

configure device

•

Industrial temperature range available; supports

demanding embedded applications

Output Features

•

1 - 0.7V current mode differential HCSL output pairs

Key Specifications

•

Cycle-to-cycle jitter < 100 ps

•

PCIe Gen2 phase jitter < 3.0ps RMS

•

PCIe Gen3 phase jitter < 1.0ps RMS

Block Diagram

VDD

SS1

Control

Logic

Phase Lock

Loop

CLK

25 MHz

crystal /clock

Clock

Buffer/

Crystal

Oscillator

Crystal Tuning Capacitors

GND

(IREF)

IDT®

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41234

MAY 5, 2017

5V41234

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Pin Assignment

VDD

Spread Spectrum Select Table

SS1

Spread%

-0.5% down

No spread

GND

CLK

GND

VDDA

SS1

IREF

16-pin QFN

Pin Descriptions

Number

Name

Pin Type

Pin Description

GND

SS1

IREF

VDDA

GND

CLK

VDD

GND

Power

–

Power

Input

Output

–

Power

Output

–

Power

–

Connect to ground.

Crystal or clock input. Connect to 25MHz crystal or single-ended clock.

Crystal connection. Connect to parallel mode crystal. Leave floating if X1 is driven by

single-ended clock.

No connect.

Connect to ground.

Spread Select 1. See table above. Internal pull-up resistor.

475 precision resistor must be attached to this pin, which is connected to internal

current source.

No connect.

Connect to 3.3V and filter as analog supply.

Connect to ground.

HCSL complementary output clock.

HCSL true output clock.

No connect.

Connect to 3.3V for OSC and digital circuits.

No connect.

IDT®

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41234

MAY 5, 2017

5V41234

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Applications Information

External Components

A minimum number of external components are required for

proper operation.

Output Structures

IREF

=2.3 mA

6*IREF

Decoupling Capacitors

Decoupling capacitors of 0.01F should be connected

between VDD and the ground plane (pin 4) as close to the

VDD pin as possible. Do not share ground vias between

components. Route power from power source through the

capacitor pad and then into IDT pin.

Crystal

A 25 MHz fundamental mode parallel resonant crystal with

= 16pF should be used. This crystal must have less than

300 ppm of error across temperature in order for the

5V41234 to meet PCI Express specifications.

475



See Layout

Guidelines

Crystal Capacitors

Crystal capacitors are connected from pins X1 to ground

and X2 to ground to optimize the accuracy of the output

frequency.

= Crystal’s load capacitance in pF

Crystal Capacitors (pF) = (C

- 8) * 2

For example, for a crystal with a 16 pF load cap, each

external crystal cap would be 16pF. (16-8)*2=16.

Current Source (Iref) Reference Resistor - R

If board target trace impedance (Z) is 50, then R

= 475

(1%), providing IREF of 2.32mA. The output current (I

) is

equal to 6*IREF.

General PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1. Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible.

2. No vias should be used between decoupling capacitor

and VDD pin.

3. The PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from the

device is less critical.

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (any ferrite beads and bulk decoupling capacitors can

be mounted on the back). Other signal traces should be

routed away from the 5V41234.This includes signal traces

just underneath the device, or on layers adjacent to the

ground plane layer used by the device.

Output Termination

The PCI-Express differential clock outputs of the 5V41234

are open source drivers and require an external series

resistor and a resistor to ground. These resistor values and

their allowable locations are shown in detail in the

PCI-Express Layout Guidelines

section.

The 5V41234 can also be terminated to LVDS compatible

voltage levels. See Layout Guidelines section.

IDT®

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41234

MAY 5, 2017

5V41234

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Layout Guidelines for PCI Express

PCIe Reference Clock

Common Recommendations for Differential Routing

Dimension or Value

L1 length, route as non-coupled 50ohm trace

0.5 max

L2 length, route as non-coupled 50ohm trace

0.2 max

L3 length, route as non-coupled 50ohm trace

0.2 max

49.9

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace

L4 length, route as coupled stripline 100ohm differential trace

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace

L4 length, route as coupled stripline 100ohm differential trace

Unit

inch

ohm

Figure

2 min to 16 max

1.8 min to 14.4 max

inch

0.25 to 14 max

0.225 min to 12.6 max

inch

Figure 1: Down Device Routing

L4'

L1'

HCSL Output Buffer

L2'

PCI Express

Down Device

REF_CLK Input

L3'

Figure 2: PCI Express Connector Routing

L4'

L1'

HCSL Output Buffer

L2'

PCI Express

Add-in Board

REF_CLK Input

L3'

IDT®

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41234

MAY 5, 2017

5V41234

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Layout Guidelines for LVDS and Other Applications

Alternative Termination for LVDS and other Common Differential Signals (figure 3)

Vdiff

Vp-p

Vcm

Note

0.45v

0.22v

1.08

150

100

0.58

0.28

0.6

78.7

137

100

0.80

0.40

0.6

78.7

none

100

ICS874003i-02 input compatible

0.60

0.3

1.2

174

140

100

Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Figure 3

R1a

L4'

L1'

R1b

HCSL Output Buffer

L2'

R2a

R2b

Down Device

REF_CLK Input

L3'

Cable Connected AC Coupled Application (figure 4)

Component

Value

Note

R5a, R5b

8.2K 5%

R6a, R6b

1K 5%

0.1 µF

Vcm

0.350 volts

Figure 4

3.3 Volts

R5a

L4'

R6a

R5b

R6b

PCIe Device

REF_CLK Input

IDT®

1 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41234

MAY 5, 2017

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5V41234NLGI Related Products

	5V41234NLGI	5V41234NLG
Description	VFQFPN-16, Tube	VFQFPN-16, Tube
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN	VFQFPN
package instruction	HVQCCN, LCC16,.12SQ,20	HVQCCN, LCC16,.12SQ,20
Contacts	16	16
Manufacturer packaging code	NLG16P2	NLG16P2
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Samacsys Description	VFQFN- N 3 X 3 X 1.0 MM - NO LEAD	VFQFN- N 3 X 3 X 1.0 MM - NO LEAD
JESD-30 code	S-XQCC-N16	S-XQCC-N16
JESD-609 code	e3	e3
length	3 mm	3 mm
Humidity sensitivity level	3	3
Number of terminals	16	16
Maximum operating temperature	85 °C	70 °C
Maximum output clock frequency	100 MHz	100 MHz
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC16,.12SQ,20	LCC16,.12SQ,20
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Master clock/crystal nominal frequency	25 MHz	25 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm
Maximum slew rate	70 mA	70 mA
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	3 mm	3 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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