HY57V641620HGTP-H datasheet, PDF

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HY57V641620HGTP-H: DescriptionSynchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size221KB，12 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HY57V641620HGTP-H Overview

Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

HY57V641620HGTP-H Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e6
length	22.238 mm
memory density	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.194 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.002 A
Maximum slew rate	0.15 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Bismuth (Sn/Bi)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	10.16 mm

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HY57V641620HG(L)TP

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V641620HG(L)TP is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications

which require large memory density and high bandwidth. HY57V641620HG(L)TP is organized as 4banks of 1,048,576x16.

HY57V641620HG(L)TP is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are

synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input

and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

Note)

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

All inputs and outputs referenced to positive edge of system

clock

Data mask function by UDQM or LDQM

Internal four banks operation

•

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

Package Type: 54Pin TSOPII(Lead Free)

•

ORDERING INFORMATION

Part No.

HY57V641620HGTP-5/55/6/7

HY57V641620HGTP-K

HY57V641620HGTP-H

HY57V641620HGTP-8

HY57V641620HGTP-P

HY57V641620HGTP-S

HY57V641620HGLTP-5/55/6/7

HY57V641620HGLTP-K

HY57V641620HGLTP-H

HY57V641620HGLTP-8

HY57V641620HGLTP-P

HY57V641620HGLTP-S

Clock Frequency

200/183/166/143MHz

133MHz

125MHz

100MHz

200/183/166/143MHz

133MHz

125MHz

100MHz

Power

Organization

Interface

Package

Normal

4Banks x 1Mbits x16

LVTTL

400mil 54pin TSOP II

(Lead or Lead Free)

Low

power

Note : VDD(Min) of HY57V641620HG(L)TP-5/55/6 is 3.135V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use

of circuits described. No patent licenses are implied.

Rev. 0.9 / Mar. 2004

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