TSC21020F-20SBSL3 datasheet, PDF

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TSC21020F-20SBSL3: DescriptionFloating Point Processor, 40-Bit, CMOS, CQFP256, CERAMIC, MQFP-256; CategoryThe embedded processor and controller Microcontrollers and processors; File Size717KB，37 Pages; ManufacturerAtmel (Microchip)

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TSC21020F-20SBSL3 Overview

Floating Point Processor, 40-Bit, CMOS, CQFP256, CERAMIC, MQFP-256

TSC21020F-20SBSL3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	QFP
package instruction	QFF, QFL256,2.1SQ,20
Contacts	256
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
bit size	32
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	40
Format	FLOATING POINT
JESD-30 code	S-CQFP-F256
JESD-609 code	e0
length	37.085 mm
low power mode	NO
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output data bus width	40
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Encapsulate equivalent code	QFL256,2.1SQ,20
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
Maximum seat height	3.18 mm
Maximum slew rate	430 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	0.508 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	100k Rad(Si) V
width	37.085 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, FLOATING POINT PROCESSOR

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TSC21020F

Radiation Tolerant 32/40–Bit IEEE Floating–Point

DSP Microprocessor

Introduction

TEMIC Semiconductors is manufacturing a radiation

tolerant version of the Analog Devices ADSP–21020

32/40–Bit Floating–Point DSP.

The product is pin and code compatible with ADI

product, making system development straight forward

and cost effective, using existing development tools and

algorithms.

Features

Superscalar IEEE Floating-Point-Processor

Off-Chip Harvard Architecture Maximizes Signal Processing

Performance

50 ns, 20 MIPS Instruction Rate, Single-Cycle Execution

60 MFLOPS Peak, 40 MFLOPS Sustained Performance

1024-Point Complex FFT Benchmark : 0.975 ms

Divide (y/x) : 300 ns

Inverse Square Root (1/√x) : 450 ns

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats

32-Bit Fixed-Point Formats, Integer and Fractional, with

80-Bit Accumulators

IEEE Exception Handling with Interrupt on Exception

Three Independent Computation Units : Multiplier, ALU,

and Barrel Shifter

Dual Data Address Generators with Indirect, Immediate,

Modulo, and Bit Reverse Addressing Modes

Two Off-Chip Memory Transfers in Parallel with Instruction

Fetch and Single-Cycle Multiply & ALU Operations

Multiply with Add & Subtract for FFT Butterfly

Computation

Efficient Program Sequencing with Zero-Overhead

Looping : Single-Cycle Loop Setup

Single-Cycle Register File Context Switch

23 ns External RAM Access Time for Zero-Wait-State, 40 ns

Instruction Execution

IEEE JTAG Standard 1149.1 Test Access Port and On-Chip

Emulation Circuitry

223 CPGA package for breadboarding

256 Multi layer quad flat pack, flat leads, for flight models

Full compatible with Analog Devices ADSP-21020

Latch up immune

Total dose better than 100 Krad (Si)

SEU immunity better than 50 MeV/mg/cm

For 25 MHz specification, call factory

– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO

– Product licensed from Analog Devices Inc.

Rev. E – Oct. 05, 1998

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