PLS163N datasheet, PDF - EEWORLD Datasheet

PLS163N: DescriptionIC FPGA, PDIP24, Field Programmable Gate Array; CategoryProgrammable logic devices Programmable logic; File Size171KB，6 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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PLS163N Overview

IC FPGA, PDIP24, Field Programmable Gate Array

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NXP
package instruction	DIP, DIP24,.3
Reach Compliance Code	unknown
Architecture	PAD-TYPE
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
Number of entries	12
Output times	9
Number of product terms	9
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL

	PLS163N
Description	IC FPGA, PDIP24, Field Programmable Gate Array
Is it Rohs certified?	incompatible
Maker	NXP
package instruction	DIP, DIP24,.3
Reach Compliance Code	unknown
Architecture	PAD-TYPE
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
Number of entries	12
Output times	9
Number of product terms	9
Number of terminals	24
Maximum operating temperature	70 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL

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