Integrated
Circuit
Systems, Inc.
ICS94235
Recommended Application:
Output Features:
•
1 - Differential pair open drain CPU clocks
•
1 - Single-ended open drain CPU clock
•
13 - SDRAM @ 3.3V
•
7 - PCI @ 3.3V
•
2 - AGP @ 3.3V
•
1 - 48MHz, @3.3V
•
1 - REF @ 3.3V, (selectable strength) through I
2
C
Features:
•
Programmable ouput frequency
•
Programmable ouput rise/fall time
•
Programmable CPU, SDRAM, PCI and AGP skew
•
Real time system reset output
•
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
•
Watchdog timer technology to reset system
if over-clocking causes malfunction
•
Uses external 14.318MHz crystal
Skew Specifications:
•
CPUT - CPUC: <250ps
•
PCI - PCI: <500ps
•
CPU - SDRAM: <350ps
•
SDRAM - SDRAM: <250ps
•
AGP - AGP: <250ps
•
AGP - PCI: <750ps
•
CPU - PCI: <3ns
RESET#
*PD#
GND
X1
X2
AVDD
**FS0/REF0
VDD
**FS1/AGP0
AGP1
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDD
*MODE/PCICLK3
PCICLK4
PCICLK5
AVDD48
**FS3/48MHz
GND
SCLK
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CPUCLKT0
CPUCLKC0
CPUCLKT1
SDATA
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
GND
SDRAM6
SDRAM7
SDRAM8
SDRAM9
GND
VDD
SDRAM10(PCI_STOP#)*
SDRAM11
SDRAM12
48-Pin 300mil SSOP &
240mil TSSOP package
Block Diagram
PLL2
48MHz
Functionality
FS 3
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
FS 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CP U S DRAM
66.66
66.66
66.66 100.00
100.00 66.66
100.00 100.00
100.00 133.33
120.00 120.00
133.33 100.00
133.33 133.33
90.00
90.00
100.90 100.90
100.00 66.66
100.00 100.00
100.00 133.33
126.00 126.00
133.33 100.00
133.33 133.33
PCI
33.33
33.33
33.33
33.33
33.33
30.00
33.33
33.33
30.00
33.63
33.33
33.33
33.33
31.50
33.33
33.33
AGP
66.66
66.66
66.66
66.66
66.66
60.00
66.66
66.66
60.00
67.27
66.66
66.66
66.66
63.00
66.66
66.66
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
REF0
CPU
DIVDER
2
CPUCLKT (1:0)
CPUCLKC0
SDRAM
DIVDER
Stop
13
SDRAM (12:0)
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
MODE
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
6
PCICLK (5:0)
PCICLK_F
AGP
DIVDER
Stop
2
AGP (1:0)
RESET#
Power Groups
94235 Rev A 01/17/02
Third party brands and names are the property of their respective owners.
ICS94235
Pin Descriptions
PIN NUMBER
1
PIN NAME
RESET#
TYPE
OUT
DESCRIPTION
Real time system reset signal for frequency value or watchdog timmer
timeout. This signal is active low.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318M Hz.
Ground pins
Power supply pins, nominal 3.3V
Analog power supply pin, nominal 3.3V
Frequency select pin.
14.318 M Hz reference clock.
Frequency select pin.
AGP outputs defined as 2X PCI. These may not be stopped.
AGP outputs defined as 2X PCI. These may not be stopped.
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
PCI clock outputs.
PCI clock output.
Function select pin, 1=Desktop M ode, 0=M obile M ode.
Analog power supply pin, nominal 3.3V
Frequency select pin.
48M Hz output clock
Clock input of I C input, 5V tolerant input
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM clock output.
SDRAM clock outputs.
Data pin for I C circuitry 5V tolerant
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
2
2
2
4
5
3, 11, 16, 23, 29,
34, 41, 48
8, 17, 28, 35, 40
6
7
9
10
12
20, 19, 15, 14, 13
18
21
22
24
27
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
44
45, 47
46
PD#
X1
X2
1
IN
IN
OUT
PWR
PWR
PWR
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
OUT
IN
1
GND
VDD
AVDD
FS0
REF0
2, 3
FS1
AGP0
AGP1
PCICLK_F
FS2
PCICLK
(5:4) (2:0)
PCICLK3
M ODE
AVDD48
FS3
48M Hz
SCLK
PCI_STOP#
SDRAM 10
SDRAM
(12:11, 9:0 )
SDATA
CPUCLKT (1:0)
CPUCLKC0
2, 3
1, 3
1, 3
2, 3
IN
OUT
OUT
I/O
OUT
OUT
Third party brands and names are the property of their respective owners.
ICS94235
General Description
Mode Pin - Power Management Input Control
MODE, Pin 18
(Latched Input)
0
1
Pin 27
PCI_STOP#
(Input)
SDRAM10
(Output)
Third party brands and names are the property of their respective owners.
ICS94235
General I
2
C serial interface information for the ICS94235
How to Write:
How to Read:
How to Write:
Controller (Host)
Start Bit
Address D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address D3
(H )
ICS (Slave /Receive r)
ACK
ACK
A CK
Byte Count
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B8
ACK
Byte 7
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
If 12
H
has been written to B8
ACK
If 13
H
has been written to B8
ACK
If 14
H
has been written to B8
ACK
Stop Bit
Byte18
Byte 19
Byte 20
Third party brands and names are the property of their respective owners.
ICS94235
Brief I
2
C registers description for ICS94235
Programmable System Frequency Generator
Register Name
Functionality & Frequency
Select Register
Output Control Registers
Vendor ID & Revision ID
Registers
Byte
0
Description
Output frequency, hardware / I C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00
H
to this byte.
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog enable, watchdog status and
programmable
’safe’
frequency’ can be
configured in this register.
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
These registers control the spread
percentage amount.
Increment or decrement the group skew
amount as compared to the initial skew.
These registers will control the output
rise and fall time.
2
PWD Default
See individual
byte description
See individual
byte description
See individual
byte description
1-6
7
Byte Count
Read Back Register
Watchdog Timer
Count Register
8
08
H
9
10
H
Watchdog Control Registers 10 Bit [6:0]
000,0000
VCO Control Selection Bit
10 Bit [7]
0
VCO Frequency Control
Registers
Spread Spectrum Control
Registers
Group Skews Control
Registers
Output Rise/Fall Time
Select Registers
11-12
Depended on
hardware/byte 0
configuration
Depended on
hardware/byte 0
configuration
See individual
byte description
See individual
byte description
13-14
15-16
17-20
Third party brands and names are the property of their respective owners.
51mcu
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