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AS7C34098A-15B2C

Description
Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 6 X 9 MM, FBGA-48
Categorystorage    storage   
File Size320KB,12 Pages
ManufacturerAlliance Memory
Download Datasheet Parametric View All

AS7C34098A-15B2C Overview

Standard SRAM, 256KX16, 15ns, CMOS, PBGA48, 6 X 9 MM, FBGA-48

AS7C34098A-15B2C Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAlliance Memory
Parts packaging codeBGA
package instructionTFBGA,
Contacts48
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time15 ns
JESD-30 codeR-PBGA-B48
JESD-609 codee0
length9 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals48
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX16
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width6 mm
February 2004
®
AS7C34098A
3.3 V 256 K × 16 CMOS SRAM
Features
• Pin compatible with AS7C34098
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
- 48-ball FBGA 6 x 9 mm
• Low power consumption: ACTIVE
- 650 mW /max @ 10 ns
• ESD protection
2000 volts
• Latch-up current
200 mA
• Low power consumption: STANDBY
- 18 mW /max CMOS
• Individual byte read/write controls
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
V
CC
1024 × 256 × 16
Array
(4,194,304)
GND
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
A0
A1
A2
A3
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
I/O
buffer
Row Decoder
Control circuit
Column decoder
A5
A9
A10
A11
A14
A15
A16
A17
UB
OE
LB
CE
Selection guide
–10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Industrial
Commercial
10
4
180
170
5
–12
12
5
160
150
5
–15
15
6
140
130
5
–20
20
7
110
100
5
Unit
ns
ns
mA
mA
mA
2/12/04, v. 1.2
Alliance Semiconductor
P. 1 of 12
Copyright © Alliance Semiconductor. All rights reserved.

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