Errata
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Wake-up from Power Save Executes Instructions before Interrupt
SPI can Send Wrong Byte
Wrong Clearing of EXTRF in MCUSR
Reset during EEPROM Write
SPI Interrupt Flag can be Undefined after Reset
Serial Programming at Voltages below 3.4V
Skip Instruction with Interrupts
Signature Bytes
Read Back Value during EEPROM Polling
MISO Active during In-System Programming
The ADC has no Free-running Mode
UART Loses Synchronization if RXD Line is Low when UART Receive is Disabled
12. Wake-up from Power Save Executes Instructions before Interrupt
When waking up from power save, some instructions are executed before the
interrupt is called. If the device is woken up by an external interrupt, 2 instruction
cycles are executed. If it is woken up by the asynchronous timer, 3 instructions
are executed before the interrupt.
Problem Fix/Workaround
Make sure that the first two or three instructions following sleep are not dependent
on the executed interrupt.
11. The SPI can Send Wrong Byte
If the SPI is in Master mode, it will restart the old transfer if new data is written on
the same clock edge as the previous transfer is finished.
Problem Fix/Workaround
When writing to the SPI, first wait until it is ready, then write the byte to transmit.
10. Wrong Clearing of EXTRF in MCUSR
The EXTRF flag in MCUSR will be cleared when clearing the PORF-flag. The flag
does not get cleared by writing a “0” to it.
Problem Fix/Workaround
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega103L
Rev. F/G
Errata Sheet
Finish the test of both flags before clearing any of them. Clear both flags simulta-
neously
by writing “0” to both PORF and EXTRF in MCUCR.
9. Reset during EEPROM Write
If reset is activated during EEPROM write, the result is not what should be
expected. The EEPROM write cycle completes as normal, but the address regis-
ters are reset to 0. The result is that both the address written and address 0 in the
EEPROM can be corrupted.
Problem Fix/Workaround
Avoid using address 0 for storage, unless you can guarantee that you will not get
a reset during EEPROM write.
Rev. 1197D–12/99
1
8. SPI Interrupt Flag can be Undefined after Reset
In certain cases when there are transitions on the SCK
pin during reset, or the SCK pin is left unconnected, the
start-up value of the SPI interrupt flag is unknown. If
the flag is not reset before enabling the SPI interrupt, a
pending SPI interrupt may be executed.
Problem Fix/Workaround
Clear the SPI interrupt flag before enabling the
interrupt.
7. Serial Programming at Voltages below 3.4V
At voltages below 3.4V, serial programming might fail.
Problem Fix/Workaround
Keep V
CC
above 3.4V during In-System Programming.
6. Skip Instruction with Interrupts
A skip instruction (SBRS, SBRC, SBIS, SBIC, CPSE)
that skips a two-word instruction needs three clock
cycles. If an interrupt occurs during the first or second
clock cycle of this skip instruction, the return address
will not be stored correctly on the stack. In this situa-
tion, the address of the second word in the two-word
instruction is stored. This means that on return from
interrupt, the second word of the two-word command
will be decoded and executed as an instruction. The
ATmega103L has four two-word instructions: LDS,
STS, JMP and CALL.
Notes:
1. This can only occur if all of the following conditions
are true:
- A skip instruction is followed by a two-word
instruction.
- The skip instruction is actually skipping the
two-word instruction.
- Interrupts are enabled, and at least one interrupt
source can generate an interrupt.
- An interrupt arrives in the first or second cycle of the
skip instruction.
2. This will only cause problems if the address of the
following LDS or STS command points to an address
beyond 400 Hex.
5. Signature Bytes
The signature bytes of the first few lots of the
ATmega103L have been shipped with wrong signature
bytes. Also in the datasheet, the wrong signature bytes
has been given. The correct signature bytes are: $1E
$97 $01.
Problem Fix/Workaround
Programmers must allow both $1E $97 $01 and $1E
$01 $01 as valid signature bytes.
4. Read Back Value during EEPROM Polling
When a new EEPROM byte is being programmed into
the EEPROM with In-System Programming, reading
the address location being programmed will give the
value P1 (see table 1) until the Auto-erase is finished.
Then the value P2 will follow until programming is fin-
ished. At the time the device is ready for a new
EEPROM byte, the programmed value will read
correctly.
Table 1.
Address Location
Revision
F
G
Note:
P1
$7F
$80
P2
$7F
$7F
This is only a problem for In-System Programmers.
Reading and writing the EEPROM during normal opera-
tion is not affected by this.
Problem Fix/Workaround
Programmers must allow both $80 and $7F as read
back values if data polling is used for the EEPROM.
Polling will not work for either of the values P1 and P2,
so when programming these values, the user will have
to wait the prescribed time t
WD_EEPROM
before program-
ming the next byte.
3. MISO Active during In-System Programming
During In-System Programming, the MISO line (pin 13)
of the ATmega103L is active, although the UART pins
are used for programming. If pin 13 is used as an input
in the application, a collision may occur on this line.
Problem Fix/Workaround
- If the MISO pin is used as an input, make sure that
there is a current-limiting resistor in series with the line.
- If the pin is used as an output, make sure that what-
ever is connected to the line can accept that the pin is
toggling during programming.
Problem Fix/Workaround
For C-programs, use the IAR compiler version 1.40b or
later. The compiler will never generate the sequence.
For assembly program, avoid skipping a two-word
instruction if interrupts are enabled.
2
ATmega103L
ATmega103L
2. The ADC has no Free-running Mode
E a r l y v e r s i o ns of th e A Tm e g a1 0 3 L d a t as h e e t
described an ADC Free-running Mode. This mode is
not available in this device, and bit number 5 in the
ADCSR register must always be written as “0”.
Problem Fix/Workaround
Use Single-conversion Mode and always use the latest
revision of the datasheet.
1. UART Loses Synchronization if RXD Line is Low
when UART Receive is Disabled
The UART will detect a UART start bit and start recep-
tion even if the UART is not enabled. If this occurs, the
first byte after re-enabling the UART will be corrupted.
Problem Fix/Workaround
Make sure that the RX line is high at start-up and when
the UART is disabled. An external RS232-level con-
verter keeps the line high during start-up.
3
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