P4080/P4081
QorIQ Integrated Processor
Hardware Specifications
DS1066
The P4080/P4081 QorIQ integrated communication pro-
cessor combines eight Power Architecture
®
processor
cores with high-performance data path acceleration logic
and network and peripheral bus interfaces required for
networking, telecom/datacom, wireless infrastructure,
and mil/aerospace applications.
This chip can be used for combined control, data path,
and application layer processing in routers, switches, base
station controllers, and general-purpose embedded com-
puting. Its high level of integration offers significant
performance benefits compared to multiple discrete
devices, while also greatly simplifying board design.
This chip includes the following function and features:
•
Eight e500-mc Power Architecture cores, each with a
•
Eight 1-Gigabit Ethernet controllers
•
Two 64-bit DDR2/DDR3 SDRAM memory controllers
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
backside 128 Kbyte L2 cache with ECC
– Three levels of instructions: user, supervisor, and
hypervisor
– Independent boot and reset
– Secure boot capability
CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet end-points
A frontside 2 MB L3 Cache with ECC
CoreNet bridges between the CoreNet fabric the I/Os,
data path accelerators, and high and low
speed peripheral interfaces
Two 10-Gigabit Ethernet (XAUI) controllers
One 10-Gigabit Ethernet (XAUI) controller on P4081
•
•
with ECC
Multicore programmable interrupt controller (MPIC)
Four I
2
C controllers
Four 2-pin UARTs or two 4-pin UARTs
Two 4-channel DMA engines
Enhanced local bus controller (eLBC)
Three PCI Express 2.0 controllers/ports
Two serial RapidIO
®
1.2 controllers/ports
Enhanced secure digital host controller (SD/MMC)
Enhanced serial peripheral interfaces (eSPI)
High-speed USB controller (USB 2.0)
– Host and device support
– Enhanced host controller interface (EHCI)
– ULPI interface to PHY
Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following
functions:
– Frame manager (FMan) for packet parsing,
classification, and distribution
– Queue manager (QMan) for scheduling, packet
sequencing, and congestion management
– Hardware buffer manager (BMan) for buffer
allocation and de-allocation
– Encryption/decryption (SEC 4.0)
– Regex pattern matching (PME 2.0)
1295 FC-PBGA package
Whilst Teledyne e2v Semiconductors SAS has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the
consequences of any use thereof and also reserves the right to change the specification of goods without notice. Teledyne e2v Semiconductors SAS accepts no
liability beyond the set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of the devices in accordance with
information contained herein.
Teledyne e2v Semiconductors SAS, avenue de Rochepleine 38120 Saint-Egrève, France
Telephone: +33 (0)4 76 58 30 00
Contact Teledyne e2v by e-mail: hotline-std@teledyne-e2v.com or visit www.teledyne-e2v.com for global sales and operations centres
Holding Company: Teledyne e2v Semiconductors SAS
Teledyne e2v Semiconductors SAS 2019
1066H–HIREL–03/19
P4080/P4081
This figure shows the major functional units within the chip.
Figure 0-1.
P4080/P4081 QorIQ Preliminary Block Diagram
1024 KB
frontside
L3 cache
128 KB
backside
L2 cache
eOpenPIC
PreBoot
loader
Security
monitor
Internal
BootROM
Power mgmt
SD/MMC
SPI
2x DUART
4x I2C
2x
USB 2.0/ULPI
2x
RGMII
Clocks/Reset
GPIO
CCSR
18-Lane (10/4/4) 5 Gbps SerDes
1 On P4081, the 10GE is only on FM2 (de-featured on FM1)
Test
port/
SAP
Pattern
match
engine
2.0
Buffer
Mgr
eLBC
Security
4.0
Queue
Mgr
Frame Manager
Parse, classify,
distribute
Buffer
1GE 1GE
10GE
1GE 1GE
Frame Manager
Parse, classify,
distribute
Buffer
1GE 1GE
1GE 1GE
Perf CoreNet
monitor trace
Aurora
RapidIO
message
unit
(RMU)
2x DMA
PAMU
PAMU
PAMU
CoreNet ™
Coherency fabric
PAMU
PAMU
Peripheral
access mgmt unit
Power Architecture®
e500mc core
32 KB
D-cache
32 KB
I-cache
1024 KB
frontside
L3 cache
64-bit
DDR2/DDR3
memory controller
64-bit
DDR2/DDR3
memory controller
P4080/P4081
Real-time debug
Watchpoint
cross
trigger
10GE1
PCIe PCIe
sRIO PCIe
sRIO
1.
1.1
PIN ASSIGNMENTS AND RESET STATES
1295 FC-PBGA Ball Layout Diagrams
These figures show the FC-PBGA ball map.
2
1066H–HIREL–03/19
Teledyne e2v Semiconductors SAS 2019
P4080/P4081
Figure 1-1.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
D2_
MDQ
[16]
D2_
MDQS
[2]
D2_
MDQ
[22]
D2_
MDQ
[19]
D1_
MCK
[4]
D2_
MCK
[4]
D2_
MDQ
[31]
D2_
MECC
[0]
D2_
MDQS
[8]
D2_
MDQS
[8]
D2_
MBA
[2]
1295 BGA Ball Map Diagram (Top View)
3
D2_
MDQ
[20]
D2_
MDQ
[17]
GND
[1]
D2_
MDQ
[18]
D2_
MDQ
[29]
GND
[3]
D2_
MDM
[3]
D2_
MDQ
[30]
GND
[8]
D2_
MECC
[1]
D2_
MECC
[6]
GND
[41]
2
D2_
MDQ
[21]
GVDD
[1]
D2_
MDQS
[2]
D2_
MDQ
[23]
GVDD
[12]
D1_
MCK
[4]
D2_
MCK
[4]
GVDD
[21]
D2_
MECC
[5]
D2_
MDM
[8]
GVDD
[25]
D2_MA
[15]
4
D2_
MDQ
[10]
D2_
MDQ
[11]
D2_
MDM
[2]
GVDD
[7]
D2_
MDQ
[28]
D2_
MDQ
[24]
GVDD
[16]
D2_
MDQ
[26]
D2_
MECC
[4]
GVDD
[24]
D2_
MECC
[7]
D2_
MCKE
[3]
GVDD
[28]
D2_
MCKE
[2]
D2_MA
[7]
GVDD
[34]
D2_MA
[2]
D2_
MCK
[1]
D2_
MCK
[0]
D2_MA
[0]
D2_
MDIC
[0]
GVDD
[51]
D2_MA
[13]
D1_
MDQS
[4]
GVDD
[48]
D2_
MDQ
[36]
D2_
MDQ
[32]
GVDD
[56]
D2_
MDQ
[39]
D2_
MDQ
[45]
GVDD
[61]
D2_
MDQS
[5]
D2_
MDQ
[42]
GVDD
[68]
D2_
MDQ
[60]
D2_
MDQ
[61]
5
D2_
MDQS
[1]
GND
[2]
D2_
MDQ
[14]
D2_
MDQ
[15]
GND
[4]
D2_
MDQ
[25]
D2_
MDQS
[3]
GND
[9]
D1_
MECC
[1]
D1_
MDQS
[8]
GND
[40]
D2_
MECC
[2]
D2_
MECC
[3]
GND
[43]
D2_
MCKE
[0]
D2_
MCKE
[1]
GND
[49]
D1_
MCK
[1]
D1_
MCK
[0]
GND
[52]
D1_
MDIC
[1]
D1_
MDQ
[36]
GND
[57]
D1_
MDQS
[4]
D1_
MDQ
[38]
GND
[61]
D1_
MDQ
[40]
D1_
MDQS
[5]
GND
[65]
D2_
MDQ
[44]
D2_
MDQ
[41]
GND
[68]
D2_
MDQ
[43]
D2_
MDQ
[56]
GND
[73]
D2_
MDQ
[57]
6
D2_
MDQS
[1]
D2_
MDM
[1]
GVDD
[6]
D2_
MDQ
[9]
D1_
MDQ
[22]
GVDD
[13]
D2_
MDQS
[3]
D2_
MDQ
[27]
GVDD
[22]
D1_
MDQS
[8]
D1_MA
[15]
GVDD
[27]
7
D2_
MDQ
[8]
D2_
MDQ
[13]
D2_
MDQ
[12]
GND
[5]
D1_
MDQ
[23]
D1_
MDQ
[24]
GND
[10]
D1_
MDQ
[30]
D1_
MECC
[5]
GND
[39]
8
D2_
MDQ
[3]
GVDD
[2]
D1_
MDQ
[16]
D1_
MDQS
[2]
GVDD
[11]
D1_
MDQ
[29]
D1_
MDQS
[3]
GVDD
[20]
D1_
MECC
[4]
D1_
MDM
[8]
9
D2_
MDQ
[7]
D2_
MDQ
[2]
GND
[6]
D1_
MDQS
[2]
D1_
MDQ
[18]
GND
[11]
D1_
MDQS
[3]
D1_
MDQ
[31]
GND
[38]
10
D2_
MDQS
[0]
D2_
MDQ
[6]
D1_
MDQ
[21]
GVDD
[8]
D1_
MDQ
[19]
D1_
MDQ
[28]
GVDD
[17]
D1_
MDQ
[26]
D1_
MDQ
[27]
11
D2_
MDQS
[0]
GND
[7]
D1_
MDQ
[20]
D1_
MDM
[2]
GND
[12]
D1_
MDQ
[25]
D1_
MDM
[3]
GND
[37]
NC
[28]
12
D2_
MDQ
[1]
D2_
MDM
[0]
GVDD
[5]
D1_
MDQ
[17]
D1_
MDQ
[10]
GVDD
[14]
D1_
MDQ
[11]
NC
[21]
GVDD
[35]
NC
[36]
13
D2_
MDQ
[4]
D2_
MDQ
[5]
D2_
MDQ
[0]
GND
[13]
D1_
MDQ
[14]
D1_
MDQ
[15]
GND
[35]
NC
[22]
NC
[1]
NC
[35]
VDD_PL
[63]
GND
[127]
VDD_PL
[81]
GND
[128]
VDD_PL
[88]
GND
[129]
VDD_PL
[31]
GND
[130]
VDD_PL
[59]
GND
[131]
VDD_PL
[87]
GND
[132]
VDD_PL
[82]
GND
[133]
VDD_PL
[20]
GND
[85]
IRQ
[8]
GND
[72]
IRQ
[5]
IIC3_
SCL
GND
[77]
IRQ
[7]
NC
[27]
GND
[81]
D1_
MDQ
[59]
D1_
MDQ
[58]
14
D1_
MDQ
[3]
GVDD
[3]
D1_
MDQ
[2]
D1_
MDM
[1]
GVDD
[10]
D1_
MDQS
[1]
D1_
MDQS
[1]
GVDD
[19]
NC
[14]
NC
[5]
GND
[141]
VDD_PL
[89]
GND
[140]
VDD_CA
[5]
GND
[139]
VDD_PL
[92]
GND
[138]
VDD_PL
[61]
GND
[137]
VDD_PL
[97]
GND
[136]
VDD_CB
[5]
GND
[135]
VDD_PL
[93]
GND
[134]
VDD_PL
[70]
IIC4_
SCL
IRQ
[10]
OVDD
[2]
IRQ_
OUT
IIC2_
SDA
IIC3_
SDA
IIC1_
SDA
NC
[54]
GVDD
[59]
NC
[41]
15
D1_
MDQ
[6]
D1_
MDQ
[7]
GND
[14]
D1_
MDQ
[8]
D1_
MDQ
[13]
GND
[36]
D1_
MDQ
[9]
NC
[34]
NC
[13]
NC
[33]
VDD_PL
[64]
GND
[142]
VDD_CA
[10]
GND
[143]
VDD_CA
[15]
GND
[144]
VDD_PL
[77]
GND
[145]
VDD_CB
[1]
GND
[146]
VDD_CB
[8]
GND
[147]
VDD_CB
[9]
GND
[148]
VDD_PL
[21]
GND
[149]
16
D1_
MDM
[0]
D1_
MDQS
[0]
D1_
MDQS
[0]
GVDD
[9]
NC
[3]
D1_
MDQ
[12]
GVDD
[18]
NC
[23]
NC
[16]
17
D1_
MDQ
[0]
D1_
MDQ
[5]
D1_
MDQ
[4]
D1_
MDQ
[1]
GND
[25]
NC
[52]
NC
[37]
NC
[38]
LAD
[15]
18
GND
[24]
GND
[31]
GVDD
[4]
NC
[57]
NC
[51]
NC
[40]
LA
[31]
BVDD
[9]
LAD
[13]
LAD
[14]
GND
[32]
VDD_CA
[17]
GND
[160]
VDD_CA
[18]
GND
[161]
VDD_CA
[14]
GND
[162]
VDD_PL
[62]
GND
[167]
VDD_CB
[13]
GND
[169]
VDD_CB
[14]
GND
[168]
VDD_PL
[95]
GND
[170]
VDD_PL
[60]
GND
[79]
19
AVDD_
DDR
MVREF
NC
[56]
LCS
[0]
GND
[18]
LAD
[12]
LA
[28]
LA
[29]
LA
[30]
GND
[15]
VDD_PL
[66]
GND
[178]
VDD_CA
[6]
GND
[177]
VDD_CA
[4]
GND
[176]
VDD_PL
[91]
GND
[175]
VDD_CB
[2]
GND
[174]
VDD_CB
[3]
GND
[173]
VDD_CB
[16]
GND
[172]
VDD_PL
[25]
GND
[171]
20
AVDD_
CC1
GND
[16]
NC
[39]
LCS
[1]
LCS
[2]
BVDD
[3]
LA
[25]
BVDD
[8]
LA
[26]
LA
[27]
GND
[22]
VDD_CA
[7]
GND
[179]
VDD_CA
[2]
GND
[180]
VDD_CA
[1]
GND
[181]
VDD_PL
[28]
GND
[185]
VDD_CB
[4]
GND
[183]
VDD_CB
[17]
GND
[184]
VDD_PL
[96]
GND
[182]
VDD_PL
[57]
21
AVDD_
CC2
TEMP_
CATHODE
22
GND
[21]
GND
[17]
LBCTL
LCS
[4]
BVDD
[6]
LA
[19]
LAD
[11]
LA
[20]
LAD
[10]
BVDD
[2]
GND
[19]
VDD_PL
[80]
GND
[200]
VDD_PL
[83]
GND
[199]
VDD_PL
[84]
GND
[198]
VDD_PL
[30]
GND
[197]
VDD_PL
[85]
GND
[196]
VDD_PL
[86]
GND
[195]
VDD_PL
[79]
GND
[194]
VDD_PL
[56]
23
LALE
LCS
[5]
LCLK
[1]
LAD
[9]
LAD
[8]
GND
[26]
LAD
[7]
LA
[18]
GND
[20]
LDP
[1]
VDD_PL
[68]
GND
[208]
VDD_PL
[71]
GND
[207]
VDD_PL
[72]
GND
[206]
VDD_PL
[33]
GND
[205]
VDD_PL
[34]
GND
[204]
VDD_PL
[73]
GND
[203]
VDD_PL
[74]
GND
[202]
VDD_PL
[37]
GND
[201]
24
LWE
[1]
BVDD
[1]
LCLK
[0]
LWE
[0]
BVDD
[5]
LCS
[6]
LAD
[6]
LAD
[5]
LDP
[0]
BVDD
[7]
GND
[209]
VDD_PL
[38]
GND
[210]
VDD_PL
[39]
GND
[211]
VDD_PL
[40]
GND
[212]
VDD_PL
[41]
GND
[213]
VDD_PL
[42]
GND
[214]
VDD_PL
[43]
GND
[215]
VDD_PL
[44]
GND
[216]
VDD_PL
[55]
RSRV
[24]
RSRV
[6]
RSRV
[26]
RSRV
[35]
RSRV
[33]
RSRV
[29]
RTC
SDHC_
DAT
[0]
OVDD
[12]
25
RSRV
[56]
LGPL
[0]
LGPL
[4]
LGPL
[2]
LGPL
[1]
LAD
[4]
LA
[17]
LAD
[3]
LA
[16]
26
GND
[23]
NC
[59]
NC
[6]
NC
[55]
LGPL
[5]
BVDD
[4]
LCS
[7]
LGPL
[3]
LAD
[2]
27
NC
[32]
28
SGND
[1]
29
SD_RX
[1]
SD_RX
[1]
SGND
[12]
SVDD
[15]
SD_TX
[1]
SD_TX
[1]
XGND
[13]
XGND
[15]
XGND
[18]
30
SVDD
[1]
SGND
[10]
SD_RX
[2]
SD_RX
[2]
XGND
[11]
XVDD
[11]
SD_TX
[2]
SD_TX
[2]
XVDD
[16]
XVDD
[18]
31
SD_RX
[3]
SD_RX
[3]
SVDD
[12]
SGND
[14]
SD_TX
[3]
SD_TX
[3]
XGND
[14]
XVDD
[13]
XGND
[19]
SD_TX
[7]
XVDD
[20]
SD_TX
[8]
XVDD
[22]
SD_TX
[10]
XVDD
[26]
SD_TX
[11]
XGND
[33]
XGND
[35]
SD_TX
[12]
XVDD
[33]
SD_TX
[14]
XVDD
[3]
SD_
REF_
CLK3
XGND
[6]
SD_TX
[16]
32
SGND
[2]
SVDD
[10]
RSRV
[42]
RSRV
[45]
XVDD
[8]
XGND
[12]
XVDD
[12]
XGND
[16]
XVDD
[17]
SD_TX
[7]
XGND
[23]
SD_TX
[8]
XGND
[27]
SD_TX
[10]
XGND
[31]
XVDD
[28]
RSRV
[46]
XVDD
[31]
SD_TX
[12]
XGND
[37]
33
AVDD_
SRDS1
AGND_
SRDS1
SGND
[13]
XGND
[9]
XVDD
[9]
SD_TX
[5]
SD_TX
[5]
XVDD
[14]
SD_TX
[6]
SGND
[20]
34
SVDD
[2]
SGND
[11]
SVDD
[13]
SD_TX
[4]
SD_TX
[4]
SVDD
[17]
SGND
[17]
XGND
[17]
SD_TX
[6]
SVDD
[20]
35
SD_
REF_
CLK1
SD_
REF_
CLK1
SVDD
[14]
SGND
[15]
SGND
[16]
36
SGND
[3]
SVDD
[11]
SD_RX
[4]
SD_RX
[4]
SVDD
[16]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
SD_IMP_ SVDD
CAL_RX
[9]
NC
[42]
NC
[58]
NC
[7]
GND
[28]
NC
[48]
NC
[20]
GND
[27]
SD_RX
[0]
SD_RX
[0]
XGND
[10]
XVDD
[10]
SD_TX
[0]
SD_TX
[0]
XVDD
[15]
TEMP_
ANODE
LCS
[3]
LA
[21]
LA
[22]
GND
[29]
LA
[23]
GND
[33]
LA
[24]
VDD_PL
[67]
GND
[193]
VDD_CA
[8]
GND
[192]
VDD_CA
[3]
GND
[191]
VDD_PL
[75]
GND
[190]
VDD_PL
[76]
GND
[189]
VDD_CB
[6]
GND
[188]
VDD_PL
[78]
GND
[187]
VDD_PL
[29]
GND
[186]
SD_RX SD_RX
[5]
[5]
SVDD
[18]
SGND
[18]
SD_RX SD_RX
[6]
[6]
SGND
[19]
SVDD
[19]
SEE DETAIL A
D1_
MECC
[0]
D1_
MECC
[7]
GND
[45]
GVDD
[23]
NC
[30]
GVDD
[26]
D1_
MBA
[2]
D1_
VDD_PL
MECC
[24]
[2]
D1_
MECC
[3]
GND
[113]
SENSE- SENSE-
VDD_CA GND_CA
GND
[98]
VDD_CA
[9]
GND
[156]
VDD_CA
[11]
GND
[155]
VDD_CA
[12]
GND
[154]
VDD_PL
[22]
GND
[150]
VDD_CB
[7]
GND
[152]
VDD_CB
[15]
GND
[151]
VDD_PL
[94]
GND
[153]
VDD_PL
[58]
VDD_PL
[65]
GND
[157]
VDD_CA
[16]
GND
[158]
VDD_CA
[13]
GND
[159]
VDD_PL
[90]
GND
[222]
VDD_CB
[12]
GND
[163]
VDD_CB
[10]
GND
[164]
VDD_CB
[11]
GND
[165]
VDD_PL
[23]
GND
[166]
IRQ
[6]
IRQ
[4]
EVT
[0]
EVT
[1]
SCAN_
MODE
GND
[83]
TDI
GND
[30]
SEE DETAIL B
LAD
[0]
SENSE-
GND_PL
[2]
SENSE-
VDD_PL
[2]
GND
[34]
VDD_PL
[51]
GND
[221]
VDD_PL
[32]
GND
[226]
VDD_PL
[52]
GND
[227]
NC
[62]
GND
[228]
VDD_PL
[35]
GND
[87]
VDD_PL
[36]
GND
[229]
GND
[97]
NC
[53]
NC
[50]
XGND
[20]
RSRV
[50]
RSRV
[52]
RSRV
[48]
RSRV
[54]
NC
[43]
NC
[61]
NC
[46]
NC
[49]
VDD_PL
[53]
NC
[26]
NC
[12]
NC
[2]
NC
[11]
NC
[31]
NC
[18]
NC
[19]
NC
[17]
XGND
[21]
LAD
[1]
VDD_PL
[1]
GND
[112]
VDD_PL
[2]
GND
[111]
VDD_PL
[3]
GND
[110]
VDD_PL
[4]
GND
[109]
VDD_PL
[5]
GND
[108]
VDD_PL
[6]
GND
[107]
VDD_PL
[7]
GND
[106]
NC
[10]
NC
[9]
XGND
[22]
XVDD
[21]
XGND
[25]
XGND
[28]
XVDD
[25]
XVDD
[27]
XGND
[32]
XGND
[34]
XVDD
[32]
SD_TX
[13]
XVDD
[1]
NC
[29]
NC
[4]
NC
[15]
NC
[8]
NC
[60]
NC
[47]
SD_RX SD_RX
[7]
[7]
SVDD
[21]
SGND
[21]
D1_
MECC
[6]
D1_MA
[14]
GND
[230]
VDD_PL
[13]
GND
[126]
VDD_PL
[14]
GND
[125]
VDD_PL
[15]
GND
[124]
VDD_PL
[16]
GND
[123]
VDD_PL
[17]
GND
[122]
VDD_PL
[18]
GND
[121]
VDD_PL
[19]
GND
[120]
VDD_PL
[69]
GND
[225]
VDD_PL
[45]
GND
[224]
VDD_PL
[46]
GND
[223]
VDD_PL
[47]
GND
[46]
VDD_PL
[48]
GND
[220]
VDD_PL
[49]
GND
[219]
VDD_PL
[50]
GND
[218]
VDD_PL
[54]
GND
[217]
RSRV
[19]
RSRV
[4]
XVDD
[19]
XGND
[24]
XGND
[26]
XVDD
[23]
XGND
[30]
SD_TX
[11]
XVDD
[29]
XVDD
[30]
XGND
[36]
SD_TX
[13]
XGND
[1]
XVDD
[2]
XGND
[3]
XGND
[5]
XVDD
[6]
SD_RX SD_RX
[8]
[8]
SVDD
[22]
SD_TX
[9]
XVDD
[24]
SGND
[24]
SD_RX
[11]
SVDD
[26]
SD_
REF_
CLK2
SGND
[29]
SD_RX
[13]
SVDD
[3]
SD_TX
[15]
XVDD
[4]
RSRV
[47]
SVDD
[6]
SD_RX
[16]
SGND
[9]
SGND
[32]
SGND
[22]
SD_TX
[9]
XGND
[29]
SVDD
[24]
SD_RX
[11]
SGND
[27]
SD_
REF_
CLK2
SVDD
[28]
SD_RX
[13]
SGND
[4]
SD_TX
[15]
XGND
[4]
RSRV
[44]
SGND
[7]
SD_RX SD_RX
[9]
[9]
SGND
[23]
SVDD
[23]
D2_
D2_MA
D2_MA
[12] MAPAR_ [14]
ERR
D2_MA
[9]
GVDD
[31]
D2_MA
[11]
GND
[42]
D1_
D1_
D1_MA GND
MCKE
[12]
[44] MAPAR_
[3]
ERR
D1_
D1_MA D1_MA GVDD MCKE
[30]
[9]
[11]
[2]
GVDD
[32]
D1_
MDIC
[0]
D1_MA D1_MA
[8]
[7]
GND
[48]
GND
[47]
GVDD VDD_PL
[8]
[29]
D1_
MCKE
[0]
GND
[114]
SD_RX SD_RX
[10]
[10]
SVDD
[25]
SGND
[26]
RSRV
[43]
SVDD
[27]
SGND
[25]
AGND_
SRDS2
AVDD_
SRDS2
SGND
[28]
D2_MA D2_MA
[6]
[8]
D1_
VDD_PL
MCKE
[9]
[1]
GVDD
[33]
GND
[115]
D2_MA D2_MA D2_MA
[3]
[4]
[5]
D2_MA
[1]
D2_
MCK
[2]
D2_
MCK
[3]
GVDD
[36]
D2_
MCK
[2]
D2_
MCK
[3]
GND
[50]
D2_
MCK
[1]
D2_
MCK
[0]
GND
[51]
D2_
MBA
[0]
D2_
MCS
[2]
D2_
MCAS
GND
[58]
D2_
MODT
[3]
D2_
MDQ
[37]
GND
[62]
D2_
MDQS
[4]
D2_
MDQ
[34]
GND
[66]
D2_
MDM
[5]
D2_
MDQS
[5]
GND
[67]
D2_
MDQ
[49]
D2_
MDQ
[54]
D2_
MDQ
[55]
D1_MA D1_MA
[5]
[6]
GVDD
[37]
D1_
MCK
[2]
D1_
MCK
[3]
D1_MA D1_MA
[1]
[2]
D1_
MCK
[1]
D1_
MCK
[0]
D2_
MDIC
[1]
GVDD
[38]
GND
[53]
D1_MA D1_MA VDD_PL
[26]
[3]
[4]
D1_
MCK
[2]
D1_
MCK
[3]
D1_MA
[0]
GND
[55]
D1_
MCS
[2]
D1_
MCS
[0]
GND
[59]
D1_
MCS
[1]
D1_
MCS
[3]
GND
[63]
GND
[54]
GND
[116]
GVDD VDD_PL
[10]
[40]
D1_
MBA
[1]
GND
[117]
SD_RX SD_RX
[12]
[12]
SGND
[30]
D2_
GVDD
MAPAR_
[43]
OUT
D2_
D2_MA
MBA
[10]
[1]
D2_
MRAS
D2_
MCS
[0]
D2_
MODT
[2]
D2_
MCS
[1]
D2_
MODT
[1]
D2_
MDM
[4]
D2_
MDQ
[38]
D2_
MDQ
[35]
D2_
MCK
[5]
D1_
MCK
[5]
D2_
MDQ
[52]
D2_
MDQ
[48]
D2_
MDQS
[6]
D2_
MDQS
[6]
D2_
MDQ
[50]
D2_
MWE
GVDD
[45]
D2_
MODT
[0]
D2_
MCS
[3]
GVDD
[49]
D2_
MDQ
[33]
D2_
MDQS
[4]
GVDD
[57]
D2_
MCK
[5]
D1_
MCK
[5]
GVDD
[63]
D2_
MDQ
[53]
D2_
MDM
[6]
GVDD
[42]
D2_
MDQ
[51]
D1_
GVDD
MAPAR_
[44]
OUT
D1_
GVDD D1_MA
MBA
[10]
[41]
[0]
D1_
MDQ
[37]
D1_
MDQ
[33]
GVDD
[46]
D1_
MDQ
[39]
D1_
MDQ
[34]
GVDD
[54]
D1_
MDQS
[5]
D1_
MDQ
[46]
GVDD
[60]
D2_
MDQ
[40]
D2_
MDQ
[46]
GVDD
[67]
D2_
MDM
[7]
D2_
MDQS
[7]
D2_
MDQS
[7]
GND
[56]
D1_
MDQ
[32]
D1_
MDM
[4]
GND
[60]
D1_
MDQ
[35]
D1_
MDQ
[45]
GND
[64]
D1_
MWE
GVDD
[53]
D1_
MODT
[2]
D1_MA
[13]
GVDD
[50]
D1_
MDQ
[44]
SVDD
[29]
D1_ VDD_PL
MRAS
[11]
GVDD
[52]
GND
[118]
SD_TX
[14]
XGND
[2]
SD_
REF_
CLK3
XVDD
[5]
SD_TX
[16]
XGND
[7]
SD_TX
[17]
XVDD
[34]
GND
[100]
SD_RX SD_RX
[14]
[14]
SVDD
[4]
SGND
[5]
D1_ VDD_PL
MCAS
[27]
D1_
MODT
[0]
GND
[119]
SD_RX SD_RX
[15]
[15]
SGND
[6]
SVDD
[5]
GVDD VDD_PL
[12]
[47]
D1_
MODT
[3]
D1_
MODT
[1]
GVDD
[55]
D1_
MDQ
[43]
GVDD
[39]
GVDD
[62]
D1_
MDQS
[6]
D1_
MDQ
[50]
GVDD
[65]
D1_
MDQ
[57]
D1_
MDM
[7]
AVDD_ AGND_
SRDS3 SRDS3
SVDD
[7]
SGND
[8]
SENSE- SENSE-
VDD_PL GND_PL
[1]
[1]
RSRV
[49]
RSRV
[51]
SD_IMP_ XVDD
[7]
CAL_TX
XGND
[8]
NC
[24]
SD_TX
[17]
XGND
[38]
SD_RX
[16]
SVDD
[8]
GND
[102]
SEE DETAIL C
D1_
MDM
[5]
D1_
MDQ
[41]
RSRV
[55]
GND
[71]
IRQ
[9]
D1_
MDM
[6]
GND
[76]
D1_
MDQ
[51]
NC
[45]
GND
[80]
D1_
MDQS
[7]
GVDD
[58]
D1_
MDQ
[52]
D1_
MDQ
[49]
GVDD
[64]
D1_
MDQ
[55]
D2_
MDQ
[58]
GVDD
[15]
D2_
MDQ
[59]
D1_
MDQ
[42]
GND
[70]
D1_
MDQ
[48]
D1_
MDQS
[6]
GND
[75]
D1_
MDQ
[60]
D1_
MDQ
[61]
D1_
MDQ
[56]
IRQ
[2]
IRQ
[11]
NC
[44]
SENSE- SENSE-
VDD_CB GND_CB
IIC1_
SCL
IRQ
[3]
GND
[78]
IIC4_
SDA
IIC2_
SCL
GND
[82]
TDO
IRQ
[1]
IRQ
[0]
EVT
[3]
OVDD
[4]
EVT
[4]
EVT
[2]
RSRV
[53]
DMA2_ GPIO
OVDD
DACK
[7]
[7]
[0]
IO_
MSRCID VSEL MSRCID GPIO
[2]
[0]
[4]
[4]
OVDD MSRCID DMA2_
DREQ
[3]
[1]
[0]
IO_
CLK_
GND
VSEL
[84]
OUT
[2]
IO_
VSEL
[0]
DMA1_
DACK
[0]
OVDD
[8]
GPIO
[2]
GPIO
[3]
DMA2_
DDONE
[0]
TMS
AVDD_
PLAT
GPIO
[5]
GPIO
[6]
GPIO
[0]
GND
[90]
DMA1_
DDONE
[0]
DMA1_
DREQ
[0]
ASLEEP
TEST_
SEL
SDHC_ SDHC_
DAT
CMD
[3]
GND
[89]
UART2_
SOUT
GPIO
[1]
UART2_
CTS
OVDD
[10]
UART2_
RTS
SEE DETAIL D
RSRV
[14]
RSRV
TMS
[11]
SPI_
MISO
NC
[25]
RSRV
[18]
RSRV
[7]
RSRV
[34]
RSRV
[39]
RSRV
[17]
RSRV
[25]
RSRV
[12]
RSRV
[16]
RSRV
[15]
RSRV
[37]
RSRV
[30]
RSRV
[8]
RSRV
[40]
RSRV
[20]
RSRV
[9]
RSRV
[13]
SPI_CS
[1]
GND
[96]
RSRV
[23]
RSRV
[27]
RSRV
[1]
RSRV
[22]
RSRV
[3]
RSRV
[31]
CVDD
[1]
SPI_
CLK
SD_RX SD_RX
[17]
[17]
SGND
[31]
SVDD
[30]
D1_
MDQ
[47]
D1_
MDQ
[53]
GND
[69]
D2_
MDQ
[47]
D1_
MDQ
[54]
GND
[74]
D2_
MDQ
[62]
D2_
MDQ
[63]
OVDD
[5]
RSRV
[5]
RSRV
[10]
RSRV
[2]
RSRV
[21]
RSRV
[36]
RSRV
[38]
RSRV
[28]
RSRV
[32]
EMI2_ EC_XTRNL
MDIO _TX_STMP
[2]
TSEC_
TSEC_
LV
EMI1_
1588_PULSE DD 1588_ALARM
MDC
[5]
_OUT[1]
_OUT[2]
TSEC_
TSEC_
EC_
GTX_ 1588_ALARM1588_TRIG
CLK125 _OUT[2]
_IN[2]
GND
[104]
UART1_ SDHC_
CLK
SOUT
UART1_ SDHC_
DAT
RTS
[2]
OVDD UART2_
[1]
SIN
UART1_
CTS
TCK
GND
[93]
GND
[94]
UART1_
SIN
EMI2_ EC_XTRNL EC_XTRNL LVDD
[1]
MDC _RX_STMP _RX_STMP
[2]
[1]
TSEC_
LVDD
EMI1_ RSRV
GND
1588_PULSE
[91]
[41]
MDIO
[3]
_OUT[1]
SPI_CS TSEC_ EC_XTRNL
1588_CLK_ _TX_STMP
[3]
[1]
OUT
EC2_
SPI_CS GND
GTX_
[101]
[0]
CLK
CVDD
[2]
SPI_CS
[2]
SPI_
MOSI
EC2_
TXD
[2]
EC2_
TXD
[1]
EC2_
TXD
[0]
LVDD
[2]
EC2_
TX_EN
EC2_
TXD
[3]
GND
[105]
EC2_
RXD
[2]
EC2_
RXD
[1]
GND
[95]
EC2_
RXD
[0]
EC1_
RXD
[3]
LVDD
[4]
EC2_
RXD
[3]
EC2_
RX_DV
EC2_
RX_CLK
TSEC_ TSEC_
1588_CLK 1588_TRIG
_IN[1]
_IN
LVDD
[7]
EC1_
RXD
[1]
EC1_
GTX_
CLK
LVDD
[6]
EC1_
TXD
[0]
EC1_
RX_CLK
EC1_
RXD
[0]
EC1_
TXD
[3]
EC1_
TX_EN
GND
[103]
IO_
CKSTP_
VSEL
OUT
[3]
OVDD TMP_
DETECT
[6]
GND
[88]
TRST
EC1_
RX_DV
EC1_
RXD
[2]
GND
[99]
GVDD
[66]
D1_
MDQ
[63]
D1_
MDQ
[62]
D1_
MDQS
[7]
IO_
OVDD
PORESET VSEL
[11]
[1]
GND
[92]
HRESET
GND
[86]
MDVAL
EC1_
TXD
[1]
EC1_
TXD
[2]
OVDD RESET_
AVDD_ AVDD_
POVDD
[9]
CC4
CC3
REQ
SDHC_
SYSCLK DAT
[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Signal Groups
OVDD
I/O Supply Voltage
I/O Supply Voltage
DDR DRAM I/O Supply
SPI Voltage Supply
Local Bus I/O Supply
SVDD
SerDes Core Power Supply
SerDes Transcvr Pad Supply
Platform Supply Voltage
Core Group A Supply Voltage
Core Group B Supply Voltage
AVDD_
SRDS1
AVDD_
SRDS2
AVDD_
PLAT
AVDD_
CC
SENSE-
VDD_PL
SerDes 1 PLL Supply Voltage
SerDes 2 PLL Supply Voltage
Platform PLL Supply Voltage
Core PLL Supply Voltage
Platform Voltage Sense
SENSE-
VDD_CA
SENSE-
VDD_CB
Core Group A Voltage Sense
Core Group B Voltage Sense
Reserved
Fuse Programming Override Supply
LVDD
XVDD
GVDD
VDD_
PL
VDD_
CA
VDD_
CB
RSRV
CVDD
POVDD
BVDD
3
1066H–HIREL–03/19
Teledyne e2v Semiconductors SAS 2019
P4080/P4081
Figure 1-2.
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
D2_
MDQ
[16]
D2_
MDQS
[2]
D2_
MDQ
[22]
D2_
MDQ
[19]
D1_
MCK
[4]
D2_
MCK
[4]
D2_
MDQ
[31]
D2_
MECC
[0]
D2_
MDQS
[8]
D2_
MDQS
[8]
D2_
MBA
[2]
1295 BGA Ball Map Diagram (Detail View A)
2
D2_
MDQ
[21]
GVDD
[1]
D2_
MDQS
[2]
D2_
MDQ
[23]
GVDD
[12]
D1_
MCK
[4]
D2_
MCK
[4]
GVDD
[21]
D2_
MECC
[5]
D2_
MDM
[8]
GVDD
[25]
D2_MA
[15]
3
D2_
MDQ
[20]
D2_
MDQ
[17]
GND
[1]
D2_
MDQ
[18]
D2_
MDQ
[29]
GND
[3]
D2_
MDM
[3]
D2_
MDQ
[30]
GND
[8]
D2_
MECC
[1]
D2_
MECC
[6]
GND
[41]
4
D2_
MDQ
[10]
D2_
MDQ
[11]
D2_
MDM
[2]
GVDD
[7]
D2_
MDQ
[28]
D2_
MDQ
[24]
GVDD
[16]
D2_
MDQ
[26]
D2_
MECC
[4]
GVDD
[24]
D2_
MECC
[7]
D2_
MCKE
[3]
GVDD
[28]
D2_
MCKE
[2]
D2_MA
[7]
GVDD
[34]
D2_MA
[2]
D2_
MCK
[1]
5
D2_
MDQS
[1]
GND
[2]
D2_
MDQ
[14]
D2_
MDQ
[15]
GND
[4]
D2_
MDQ
[25]
D2_
MDQS
[3]
GND
[9]
D1_
MECC
[1]
D1_
MDQS
[8]
GND
[40]
D2_
MECC
[2]
D2_
MECC
[3]
GND
[43]
D2_
MCKE
[0]
D2_
MCKE
[1]
GND
[49]
D1_
MCK
[1]
6
D2_
MDQS
[1]
D2_
MDM
[1]
GVDD
[6]
D2_
MDQ
[9]
D1_
MDQ
[22]
GVDD
[13]
D2_
MDQS
[3]
D2_
MDQ
[27]
GVDD
[22]
D1_
MDQS
[8]
D1_MA
[15]
GVDD
[27]
D1_MA
[12]
7
D2_
MDQ
[8]
D2_
MDQ
[13]
D2_
MDQ
[12]
GND
[5]
D1_
MDQ
[23]
D1_
MDQ
[24]
GND
[10]
D1_
MDQ
[30]
D1_
MECC
[5]
GND
[39]
D1_
MECC
[6]
D1_MA
[14]
GND
[44]
8
D2_
MDQ
[3]
GVDD
[2]
D1_
MDQ
[16]
D1_
MDQS
[2]
GVDD
[11]
D1_
MDQ
[29]
D1_
MDQS
[3]
GVDD
[20]
D1_
MECC
[4]
D1_
MDM
[8]
GVDD
[26]
D1_
MBA
[2]
9
D2_
MDQ
[7]
D2_
MDQ
[2]
GND
[6]
D1_
MDQS
[2]
D1_
MDQ
[18]
GND
[11]
D1_
MDQS
[3]
D1_
MDQ
[31]
GND
[38]
D1_
MECC
[0]
D1_
MECC
[7]
GND
[45]
10
D2_
MDQS
[0]
D2_
MDQ
[6]
D1_
MDQ
[21]
GVDD
[8]
D1_
MDQ
[19]
D1_
MDQ
[28]
GVDD
[17]
D1_
MDQ
[26]
D1_
MDQ
[27]
GVDD
[23]
11
D2_
MDQS
[0]
GND
[7]
D1_
MDQ
[20]
D1_
MDM
[2]
GND
[12]
D1_
MDQ
[25]
D1_
MDM
[3]
GND
[37]
NC
[28]
NC
[30]
12
D2_
MDQ
[1]
D2_
MDM
[0]
GVDD
[5]
D1_
MDQ
[17]
D1_
MDQ
[10]
GVDD
[14]
D1_
MDQ
[11]
NC
[21]
GVDD
[35]
NC
[36]
GND
[230]
VDD_PL
[13]
GND
[126]
VDD_PL
[14]
GND
[125]
VDD_PL
[15]
GND
[124]
VDD_PL
[16]
13
D2_
MDQ
[4]
D2_
MDQ
[5]
D2_
MDQ
[0]
GND
[13]
D1_
MDQ
[14]
D1_
MDQ
[15]
GND
[35]
NC
[22]
NC
[1]
NC
[35]
VDD_PL
[63]
GND
[127]
VDD_PL
[81]
GND
[128]
VDD_PL
[88]
GND
[129]
VDD_PL
[31]
GND
[130]
14
D1_
MDQ
[3]
GVDD
[3]
D1_
MDQ
[2]
D1_
MDM
[1]
GVDD
[10]
D1_
MDQS
[1]
D1_
MDQS
[1]
GVDD
[19]
NC
[14]
NC
[5]
GND
[141]
VDD_PL
[89]
GND
[140]
VDD_CA
[5]
GND
[139]
VDD_PL
[92]
GND
[138]
VDD_PL
[61]
15
D1_
MDQ
[6]
D1_
MDQ
[7]
GND
[14]
D1_
MDQ
[8]
D1_
MDQ
[13]
GND
[36]
D1_
MDQ
[9]
NC
[34]
NC
[13]
NC
[33]
VDD_PL
[64]
GND
[142]
VDD_CA
[10]
GND
[143]
VDD_CA
[15]
GND
[144]
VDD_PL
[77]
GND
[145]
16
D1_
MDM
[0]
D1_
MDQS
[0]
D1_
MDQS
[0]
GVDD
[9]
NC
[3]
D1_
MDQ
[12]
GVDD
[18]
NC
[23]
NC
[16]
17
D1_
MDQ
[0]
D1_
MDQ
[5]
D1_
MDQ
[4]
D1_
MDQ
[1]
GND
[25]
NC
[52]
NC
[37]
NC
[38]
LAD
[15]
18
GND
[24]
GND
[31]
GVDD
[4]
NC
[57]
NC
[51]
NC
[40]
LA
[31]
BVDD
[9]
LAD
[13]
LAD
[14]
GND
[32]
VDD_CA
[17]
GND
[160]
VDD_CA
[18]
GND
[161]
VDD_CA
[14]
GND
[162]
VDD_PL
[62]
SENSE- SENSE-
VDD_CA GND_CA
GND
[98]
VDD_CA
[9]
GND
[156]
VDD_CA
[11]
GND
[155]
VDD_CA
[12]
GND
[154]
VDD_PL
[22]
VDD_PL
[65]
GND
[157]
VDD_CA
[16]
GND
[158]
VDD_CA
[13]
GND
[159]
VDD_PL
[90]
GND
[222]
D1_
VDD_PL
MECC
[24]
[2]
D1_
MECC
[3]
GND
[113]
D2_
D2_MA
D2_MA
MAPAR_ [14]
[12]
ERR
D2_MA
[9]
GVDD
[31]
D2_MA
[11]
GND
[42]
D1_
D1_
MAPAR_ MCKE
[3]
ERR
D1_
D1_MA D1_MA GVDD MCKE
[30]
[9]
[11]
[2]
GVDD
[32]
D1_
MDIC
[0]
D1_MA D1_MA
[8]
[7]
GND
[48]
GND
[47]
GVDD VDD_PL
[8]
[29]
D1_
MCKE
[0]
GND
[114]
D2_MA D2_MA
[6]
[8]
D1_
VDD_PL
MCKE
[9]
[1]
GVDD
[33]
GND
[115]
D2_MA D2_MA D2_MA
[3]
[4]
[5]
D2_MA
[1]
D2_
MCK
[2]
GVDD
[36]
D2_
MCK
[2]
GND
[50]
D2_
MCK
[1]
D1_MA D1_MA
[5]
[6]
GVDD
[37]
D1_
MCK
[2]
D1_MA D1_MA
[1]
[2]
D1_
MCK
[1]
GVDD
[38]
D1_MA D1_MA VDD_PL
[26]
[3]
[4]
D1_
MCK
[2]
GND
[54]
GND
[116]
DETAIL A
4
1066H–HIREL–03/19
Teledyne e2v Semiconductors SAS 2019
P4080/P4081
Figure 1-3.
19
AVDD_
DDR
MVREF
NC
[56]
LCS
[0]
GND
[18]
LAD
[12]
LA
[28]
LA
[29]
LA
[30]
GND
[15]
VDD_PL
[66]
GND
[178]
VDD_CA
[6]
GND
[177]
VDD_CA
[4]
GND
[176]
VDD_PL
[91]
GND
[175]
1295 BGA Ball Map Diagram (Detail View B)
20
AVDD_
CC1
GND
[16]
NC
[39]
LCS
[1]
LCS
[2]
BVDD
[3]
LA
[25]
BVDD
[8]
LA
[26]
LA
[27]
GND
[22]
VDD_CA
[7]
GND
[179]
VDD_CA
[2]
GND
[180]
VDD_CA
[1]
GND
[181]
VDD_PL
[28]
21
AVDD_
CC2
TEMP_
CATHODE
22
GND
[21]
GND
[17]
LBCTL
LCS
[4]
BVDD
[6]
LA
[19]
LAD
[11]
LA
[20]
LAD
[10]
BVDD
[2]
GND
[19]
VDD_PL
[80]
GND
[200]
VDD_PL
[83]
GND
[199]
VDD_PL
[84]
GND
[198]
VDD_PL
[30]
23
LALE
LCS
[5]
LCLK
[1]
LAD
[9]
LAD
[8]
GND
[26]
LAD
[7]
LA
[18]
GND
[20]
LDP
[1]
VDD_PL
[68]
GND
[208]
VDD_PL
[71]
GND
[207]
VDD_PL
[72]
GND
[206]
VDD_PL
[33]
GND
[205]
24
LWE
[1]
BVDD
[1]
LCLK
[0]
LWE
[0]
BVDD
[5]
LCS
[6]
LAD
[6]
LAD
[5]
LDP
[0]
BVDD
[7]
GND
[209]
VDD_PL
[38]
GND
[210]
VDD_PL
[39]
GND
[211]
VDD_PL
[40]
GND
[212]
VDD_PL
[41]
25
RSRV
[56]
LGPL
[0]
LGPL
[4]
LGPL
[2]
LGPL
[1]
LAD
[4]
LA
[17]
LAD
[3]
LA
[16]
GND
[30]
VDD_PL
[69]
GND
[225]
VDD_PL
[45]
GND
[224]
VDD_PL
[46]
GND
[223]
VDD_PL
[47]
GND
[46]
26
GND
[23]
NC
[59]
NC
[6]
NC
[55]
LGPL
[5]
BVDD
[4]
LCS
[7]
LGPL
[3]
LAD
[2]
LAD
[0]
LAD
[1]
VDD_PL
[1]
GND
[112]
VDD_PL
[2]
GND
[111]
VDD_PL
[3]
GND
[110]
VDD_PL
[4]
27
NC
[32]
28
SGND
[1]
29
SD_RX
[1]
SD_RX
[1]
SGND
[12]
SVDD
[15]
SD_TX
[1]
SD_TX
[1]
XGND
[13]
XGND
[15]
XGND
[18]
XGND
[21]
XGND
[22]
XVDD
[21]
XGND
[25]
XGND
[28]
XVDD
[25]
XVDD
[27]
XGND
[32]
XGND
[34]
30
SVDD
[1]
SGND
[10]
SD_RX
[2]
SD_RX
[2]
XGND
[11]
XVDD
[11]
SD_TX
[2]
SD_TX
[2]
XVDD
[16]
XVDD
[18]
XVDD
[19]
XGND
[24]
XGND
[26]
XVDD
[23]
XGND
[30]
SD_TX
[11]
XVDD
[29]
XVDD
[30]
31
SD_RX
[3]
SD_RX
[3]
SVDD
[12]
SGND
[14]
SD_TX
[3]
SD_TX
[3]
XGND
[14]
XVDD
[13]
XGND
[19]
SD_TX
[7]
XVDD
[20]
SD_TX
[8]
XVDD
[22]
SD_TX
[10]
XVDD
[26]
SD_TX
[11]
XGND
[33]
XGND
[35]
32
SGND
[2]
SVDD
[10]
RSRV
[42]
RSRV
[45]
XVDD
[8]
XGND
[12]
XVDD
[12]
XGND
[16]
XVDD
[17]
SD_TX
[7]
XGND
[23]
SD_TX
[8]
XGND
[27]
SD_TX
[10]
XGND
[31]
XVDD
[28]
RSRV
[46]
XVDD
[31]
33
AVDD_
SRDS1
AGND_
SRDS1
SGND
[13]
XGND
[9]
XVDD
[9]
SD_TX
[5]
SD_TX
[5]
XVDD
[14]
SD_TX
[6]
SGND
[20]
SD_RX
[8]
SVDD
[22]
SD_TX
[9]
XVDD
[24]
SGND
[24]
SD_RX
[11]
SVDD
[26]
SD_
REF_
CLK2
34
SVDD
[2]
SGND
[11]
SVDD
[13]
SD_TX
[4]
SD_TX
[4]
SVDD
[17]
SGND
[17]
XGND
[17]
SD_TX
[6]
SVDD
[20]
SD_RX
[8]
SGND
[22]
SD_TX
[9]
XGND
[29]
SVDD
[24]
SD_RX
[11]
SGND
[27]
SD_
REF_
CLK2
35
SD_
REF_
CLK1
SD_
REF_
CLK1
SVDD
[14]
SGND
[15]
SGND
[16]
SD_RX
[5]
SVDD
[18]
SD_RX
[6]
SGND
[19]
SD_RX
[7]
SVDD
[21]
SD_RX
[9]
SGND
[23]
SD_RX
[10]
SVDD
[25]
SGND
[26]
RSRV
[43]
SVDD
[27]
36
SGND
[3]
SVDD
[11]
SD_RX
[4]
SD_RX
[4]
SVDD
[16]
SD_RX
[5]
SGND
[18]
SD_RX
[6]
SVDD
[19]
SD_RX
[7]
SGND
[21]
SD_RX
[9]
SVDD
[23]
SD_RX
[10]
SGND
[25]
AGND_
SRDS2
AVDD_
SRDS2
SGND
[28]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SD_IMP_ SVDD
CAL_RX
[9]
NC
[42]
NC
[58]
NC
[7]
GND
[28]
NC
[48]
NC
[20]
GND
[27]
SENSE-
GND_PL
[2]
SENSE-
VDD_PL
[2]
GND
[34]
VDD_PL
[51]
GND
[221]
VDD_PL
[32]
GND
[226]
VDD_PL
[52]
GND
[227]
SD_RX
[0]
SD_RX
[0]
XGND
[10]
XVDD
[10]
SD_TX
[0]
SD_TX
[0]
XVDD
[15]
XGND
[20]
RSRV
[50]
RSRV
[52]
RSRV
[48]
RSRV
[54]
NC
[43]
NC
[61]
NC
[46]
NC
[49]
TEMP_
ANODE
LCS
[3]
LA
[21]
LA
[22]
GND
[29]
LA
[23]
GND
[33]
LA
[24]
VDD_PL
[67]
GND
[193]
VDD_CA
[8]
GND
[192]
VDD_CA
[3]
GND
[191]
VDD_PL
[75]
GND
[190]
DETAIL B
5
1066H–HIREL–03/19
Teledyne e2v Semiconductors SAS 2019
京公网安备 11010802033920号
EEWORLD
