One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADV7160/ADV7162–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Gray Scale Error
Coding
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
CLOCK INPUTS (CLOCK,
CLOCK)
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Current, I
IN
(JTAG Inputs)
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level
Blank Level
Sync Level
Tri-Sync Level Relative to Blank
LSB Size
DAC to DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
VOLTAGE REFERENCE
Voltage Reference Range, V
REF
Input Current, I
VREF
POWER REQUIREMENTS
V
AA
I
AA3
I
AA3
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Clock and Data Feedthrough
4, 5
Glitch Impulse
DAC to DAC Crosstalk
6
0.1
–30
50
–23
Min
Typ
Max
10
±
1
±
1
±
5
(V
AA1
= +5 V; V
REF
= +1.235 V; R
SET
= 280
Ω.
IOR, IOG, IOB (R
L
= 37.5
Ω,
C
L
= 10 pF). All specifications T
MIN
to T
MAX2
unless otherwise noted.)
Units
Bits
LSB
LSB
% Gray Scale
Binary
V
V
µA
pF
V
V
µA
µA
pF
V
V
µA
pF
mA
mA
mA
mA
µA
mA
µA
mA
µA
%
V
kΩ
pF
V
µA
V
mA
mA
mA
mA
mA
mA
%/%
dB
pV secs
dB
Test Conditions/Comments
(DAC Gain Setting = 3996)
Guaranteed Monotonic
2
0.8
±
10
10
V
AA
– 1.0
V
AA
– 1.6
±
10
±
50
10
2.4
0.4
20
20
15
17.69
16.74
0.95
0
6.29
0
6.29
19.05
17.62
1.44
5
7.62
5
7.62
17.22
1
30
30
1.14
1.235
5
5
475
440
410
450
400
360
1.26
22
20.40
18.50
1.90
50
8.96
50
8.96
3
+1.4
V
IN
= 0.4 V or 2.4 V
V
IN
= 0.4 V or 2.4 V
V
IN
= 0.4 V or 2.4 V
I
SOURCE
= 400
µA
I
SINK
= 3.2 mA
(DAC Gain Setting = 3996)
Sync Disabled
Sync Enabled
0
I
OUT
= 0 mA
V
REF
= 1.235 V for Specified Performance
For 220 MHz Operation (ADV7160)
For 170 MHz Operation (ADV7160)
For 140 MHz Operation (ADV7160)
For 220 MHz Operation (ADV7162)
For 170 MHz Operation (ADV7162)
For 140 MHz Operation (ADV7162)
COMP = 0.1
µF
NOTES
1
±
5% for all versions.
2
Temperature range (T
MIN
to T
MAX
): 0°C to +70°C.
3
Pixel Port is continuously clocked with data corresponding to a linear ramp. T
J
= 100
o
C.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times
≤3
ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
6
DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
Specifications subject to change without notice.
–2–
REV. 0
ADV7160/ADV7162
TIMING CHARACTERISTICS
Parameter
f
CLOCK
t
1
t
2
t
3
t
4
f
LOADIN
2:1 Multiplexing
4:1 Multiplexing
8:1 Multiplexing
t
5
2:1 Multiplexing
4:1 Multiplexing
8:1 Multiplexing
t
6
2:1 Multiplexing
4:1 Multiplexing
8:1 Multiplexing
t
7
2:1 Multiplexing
4:1 Multiplexing
8:1 Multiplexing
t
8
t
9
t
10
τ-t
115
t
PD6
2:1 Multiplexing
4:1 Multiplexing
8:1 Multiplexing
t
12
t
13
t
14
t
15
ANALOG OUTPUTS
7
2
1
(V
AA
= +5 V; V
REF
= +1.235 V; R
SET
= 280
Ω.
IOR, IOG, IOB (R
L
= 37.5
Ω,
C
L
= 10 pF). All
3
specifications T
MIN
to T
MAX
unless otherwise noted.)
CLOCK CONTROL AND PIXEL PORT
4
220 MHz
Version
220
4.5
2.0
2.0
10
170 MHz
Version
170
5.88
2.5
2.5
10
140 MHz
Version
140
7.14
2.86
2.86
10
Units
MHz max
ns min
ns min
ns min
ns max
Conditions/Comments
Pixel CLOCK Rate
Pixel CLOCK Cycle Time
Pixel CLOCK High Time
Pixel CLOCK Low Time
Pixel CLOCK to LOADOUT Delay
LOADIN Clocking Rate
110
55
27.5
9.1
18.18
36.36
4
8
15
4
8
15
0
5
0
τ-5
9
11
15
10
5
5
0
85
42.5
21.25
11.77
23.53
47.1
5
9
18
5
9
18
0
5
0
τ-5
9
11
15
10
5
5
0
70
35
17.5
14.29
28.58
57.16
6
12
23
6
12
23
0
5
0
τ-5
9
11
15
10
5
5
0
MHz max
MHz max
MHz max
LOADIN Cycle Time
ns min
ns min
ns min
LOADIN High Time
ns min
ns min
ns min
LOADIN Low Time
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Pixel Data Setup Time
Pixel Data Hold Time
LOADOUT to LOADIN Delay
LOADOUT to LOADIN Delay
Pipeline Delay
(1
×
CLOCK = t
1
)
Pixel CLOCK to PRGCKOUT Delay
SCKIN to SCKOUT Delay
BLANK
to SCKIN Setup Time
BLANK
to SCKIN Hold Time
CLOCKs
CLOCKs
CLOCKs
ns max
ns max
ns min
ns min
Parameter
220 MHz
Version
25
1
25
2
0
170 MHz
Version
25
1
25
2
0
140 MHz
Version
25
1
25
2
0
Units
Conditions/Comments
t
16
t
17
t
18
t
SK
ns typ
ns typ
ns typ
ns max
ns typ
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Transition Time
RGB Analog Output Skew
REV. 0
–3–
ADV7160/ADV7162
MPU P
ORT
8,9
Parameter
t
19
t
20
t
21
t
22
t
238
t
249
t
259
t
269
t
27
t
28
220 MHz
Version
0
10
45
25
5
45
20
5
20
5
170 MHz
Version
0
10
45
25
5
45
20
5
20
5
140 MHz
Version
0
10
45
25
5
45
20
5
20
5
Units
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
Conditions/Comments
R/W, C0, C1 to
CE
Setup Time
R/W, C0, C1 to
CE
Hold Time
CE
Low Time
CE
High Time
CE
Asserted to Data-Bus Driven
CE
Asserted to Data Valid
CE
Disabled to Data-Bus Three-Stated
CE
Disabled to Data Invalid
Write Data (D0–D9) Setup Time
Write Data (D0–D9) Hold Time
NOTES
General Notes
1
TTL input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points.
ECL inputs (CLOCK,
CLOCK)
are V
AA
–0.8 V to V
AA
–1.8 V, with input rise/fall times
≤
2 ns, measured between the 10% and 90% points.
Timing reference points at 50% for inputs and outputs.
Analog output load
≤
10 pF.
Data-Bus (D0–D9) loaded as shown in Figure 1.
Digital output load for LOADOUT, PRGCKOUT & SCKOUT
≤
30 pF.
2
±
5% for all versions
3
Temperature range (T
MIN
to T
MAX
); 0°C to +70°C.
Notes on PIXEL PORT
4
Pixel Port consists of the following inputs:
Pixel Inputs:
RED [A, B, C, D]
GREEN [A, B, C, D]
BLUE [A, B, C, D]
Palette Selects: PS0 [A, B, C, D];
PS1[A, B, C, D]
Pixel Controls:
SYNC, BLANK, TRISYNC,
ODD/EVEN
Clock Inputs:
CLOCK,
CLOCK,
LOADIN, SCKIN
Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT
5
τ
is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode:
2:1 multiplexing;
τ
= CLOCK
×
2
= 2
×
t
1
ns
ns
4:1 multiplexing;
τ
= CLOCK
×
4
= 4
×
t
1
8:1 multiplexing;
τ
= CLOCK
×
8
= 8
×
t
1
ns
6
These fixed values for Pipeline Delay are valid under conditions where t
10
and
τ-t
11
are met. If either t
10
or
τ-t
11
are not met, the part will operate but the Pipeline
Delay is increased.
Notes on ANALOG OUTPUTS
7
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Output rise/fall time measured between the 10% and 90% points of full-scale transition.
Transition time measured from the 50% point of full scale transition to the output remaining within 2% of the final output value. (Transition time does not include
clock and data feedthrough).
Notes on MPU PORT
8
t
23
and t
24
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
9
t
25
and t
26
are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured numbers are
then extrapolated back to remove the effects of charging the 100 pF capacitor. This means that the times t
25
and t
26
, quoted in the Timing Characteristics are the
true values for the device and as such are independent of external loading capacitances.
Specifications subject to change without notice.
I
SINK
TO OUTPUT
PIN
+2.1V
100pF
I
SOURCE
Figure 1. Load Circuit for Databus Access and Relinquish Times
–4–
REV. 0
ADV7160/ADV7162
TIMING CHARACTERISTICS (Cont.)
JTAG P
ORT
2
1
(V
AA
= +5 V; V
REF
= +1.235 V;
3
R
SET
= 280
Ω.
IOR, IOG, IOB (R
L
= 37.5
Ω,
C
L
=10 pF).
All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
PLL PERFORMANCE
4
Jitter
PLL REFERENCE INPUT
PLL
REF
Frequency
V
IH
V
IL
PLL
REF
Period
PLL
REF
Duty Cycle
JTAG PERFORMANCE
TCK Frequency, t
29
TCK High Time, t
30
TCK
Low Time, t
31
TDI, TMS Setup Time, t
32
TDI, TMS Hold Time, t
33
Digital Input to
TCK
Setup Time, t
34
Digital Input to
TCK
Hold Time, t
35
TCLK to TDO Drive, t
36
TCLK to TDO Valid, t
37
TCLK to TDO Three-State, t
38
All Versions
250
900
40
2.0
0.8
25
1.67
40
60
20
15
15
15
15
15
15
0
20
5
15
Units
ps rms
kHz min
MHz max
V max
V min
ns min
µs
max
% min
% max
MHz max
ns min
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns min
ns max
Conditions/Comments
1σ
NOTES
1
TTL input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
2
±
5% for all versions.
3
Temperature range (T
MIN
to T
MAX
); 0°C to +70°C.
4
Jitter is measured by triggering on the output clock, delayed by 15
µs
and then measuring the time period from the trigger edge to the next edge of the output clock
after the delay. This measurement is repeated multiple times and the RMS value is determined.
Author: Wang Huidong, a member of Yibo Technology Expressway Media
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