EEWORLDEEWORLDEEWORLD

Part Number

Search

98ULPA877AKI-T

Description
PLL Based Clock Driver, 98ULPA Series, 10 True Output(s), 0 Inverted Output(s), PQCC40
Categorylogic    logic   
File Size159KB,14 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric View All

98ULPA877AKI-T Overview

PLL Based Clock Driver, 98ULPA Series, 10 True Output(s), 0 Inverted Output(s), PQCC40

98ULPA877AKI-T Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerRenesas Electronics Corporation
package instructionHVQCCN,
Reach Compliance Codecompliant
series98ULPA
Input adjustmentDIFFERENTIAL
JESD-30 codeS-PQCC-N40
JESD-609 codee0
length6 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals40
Actual output times10
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.04 ns
Maximum seat height1 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width6 mm
minfmax410 MHz
Integrated
Circuit
Systems, Inc.
ICS98ULPA877A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR2 DIMM logic solution
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800)
• OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• CYCLE - CYCLE jitter 40ps
Pin Configuration
1
A
B
C
D
E
F
G
H
J
K
2
3
4
5
6
52-Ball BGA
Top View
A
B
C
D
E
F
G
H
J
K
1
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
CLKC1
CLKT1
CLKT0
Block Diagram
LD or OE
OE
OS
AV
DD
(1)
3
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
CLKC5
CLKC0
4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
CLKC6
CLKT5
CLKT6
5
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
V
DDQ
POWER
DOWN
AND
LD, OS, or OE
TEST
MODE
PLL BYPASS
LOGIC
LD
CLKT0
CLKC0
39
32
40
38
37
36
35
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
34
33
31
V
DDQ
V
DDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
V
DDQ
AGND
AV
DD
V
DDQ
GND
1
2
3
4
5
6
7
8
9
10
14
15
16
17
12
11
13
18
19
20
30
29
28
27
26
25
24
23
22
21
CLKC7
CLKT7
V
DDQ
FB_INT
FB_INC
FBOUTC
FBOUTT
V
DDQ
OE
OS
CLK_INT
CLK_INC
10K
- 100K
FBIN_INT
FBIN_INC
PLL
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
V
DDQ
CLKT3
CLKT4
CLKC3
CLKC4
CLKC9
CLKT9
CLKC9
NOTE:
1. The Logic Detect (LD) powers down the device
when a logic LOW is applied to both CLK_INT and
CLK_INC.
FBOUTT
FBOUTC
40-Pin MLF
1177F—12/10/09
CLKC8
CLKT9
CLKT8
V
DDQ
CLKC8
[NXP Rapid IoT Review] Hello World project reads sensor values that are always 0
Refer to "4.3.2.5. Build a Hello World project for Rapid IoT" in the user manual to control the LED and LCD. I added a code to read the temperature sensor in while and print it to the screen [code] ge...
littleshrimp RF/Wirelessly
A few questions for help
I haven't posted for a long time, so I'll ask netizens for help with the questions I've collected recently. 1. Is there any software for duplicate image recognition (including emoticon recognition and...
sanhuasr Talking
MSP430AFE2xx series of metering analog front-end 16-bit MCU
The MSP430AFE2xx family of metering analog front ends (AFEs) is an ultra-low-power 16-bit microcontroller for metering and smart grid applications. The low-cost MSP430AFE family is part of TI's leadin...
灞波儿奔 Microcontroller MCU
A brief tutorial on DSP interrupt settings
What common tasks are needed to implement DSP interrupts? Set which non-maskable interrupts are allowed Set the interrupt sources of each non-maskable interrupt Set and enable general interrupts Desig...
fish001 DSP and ARM Processors
Request a free ZVS buck regulator evaluation board
[url=http://www.vicorpower.cn/zh-cn/new-products/zvs-buck-regulator?hmsr=eeWorld&hmpl=2019_Banner&hmcu=PI354x_950x90&hmkw=&hmci=][/url] [url=http://www.vicorpower.cn/zh-cn/new-products/zvs-buck-regula...
eric_wang Power technology
Is there any chip that can convert analog signal (potentiometer and DC voltage) into PWM dimming signal?
[align=left]Is there any chip that can convert analog signals (potentiometer and DC voltage) into PWM dimming signals? [/align]...
vinarhuang LED Zone

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号