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M32C/81 Group
1. Overview
1.3 Performance Outline
Tables 1.1 and 1.2 list performance outlines of the M32C/81 group.
Table 1.1 M32C/81 Group Performance (144-Pin Package)
CPU
Item
Basic instructions
Shortest instruction execution time
Performance
108 instructions
31.3 ns (f(BCLK)=32 MHz, V
CC
=4.2 V to 5.5 V)
50ns (f(BCLK)=20MHz, V
CC
=3.0 V to 5.5 V)
Single-chip mode, Memory expansion mode and Microprocessor mode
16 Mbytes
See Table 1.3
123 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 12 channels
Waveform generating function: 16 bits x 20 channels
Communication function (Clock synchronous serial I/O, Clock
asynchronous serial I/O, HDLC data processing, Clock synchro-
nous variable length serial I/O, IEBus
(1)
)
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus
(1)
, I
2
C bus
(2)
1 channel
Supporting CAN 2.0B specification
10-bit A/D converter: 1 circuit, 34 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt factors
Immediate transfer, Calculation transfer and Chain transfer functions
_______
_______
Operation mode
Address space
Memory capacity
Peripheral Port
function Multifunction timer
Intelligent I/O
Serial I/O
CAN module
A/D converter
D/A converter
DMAC
DMAC II
DRAMC
CRC calculation circuit
XY converter
Watchdog timer
Interrupt
Clock generating circuit
Electric
charact-
eristics
Oscillation stop detect function
Supply voltage
Power consumption
Operating ambient temperature
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
CAS-before-RAS refresh, self-refresh, EDO, FP
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*),
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator
or crystal oscillator must be connected externally
Main clock oscillation stop detect function
4.2 V to 5.5 V (f(BCLK)=32 MHz)
3.0 V to 5.5 V (f(BCLK)=20 MHz, through VDC)
3.0 V to 3.6 V (f(BCLK)=20 MHz, not through VDC)
28 mA (V
CC
=5 V, f(BCLK)=32 MHz)
17 mA (V
CC
=3.3 V, f(BCLK)=20 MHz)
470
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz, in wait mode)
340
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, through VDC in wait mode)
5.0
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, not through VDC in wait mode)
0.4
µA
(V
CC
=5 V, f(X
CIN
)=32 kHz, in stop mode)
0.4
µA
(V
CC
=3.3 V, f(X
CIN
)=32 kHz, in stop mode)
–20 to 85
o
C, –40 to 85
o
C (optional)
144-pin plastic molded LQFP
Rev.1.00 Jun. 01, 2004
page 3 of 83
Motor Drive Control（Motor Control）
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