LHWE) and Output Enable ( G); 17 address inputs, A(16:0); and
32 bidirectional data lines, DQ(15:0). E1 and E2 device enables
control device selection, active, and standby modes. Asserting
E1 and E2 enables the device, causes I
DD
to rise to its active
value, and decodes the 17 address inputs to select one of 131,072
words in the memory. W controls read and write operations.
During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
W
E2
E1
LHWE
HHWE
I/O Mode
Mode
X
X
X
H
X
X
DQ(31:16)
3-State
DQ(15:0)
3-State
DQ(31:16)
3-State
DQ(15:0)
3-State
DQ(31:16)
3-State
DQ(15:0)
Data Out
Standby
X
X
L
X
X
X
Standby
Figure 2. 10ns SRAM Pinout (68)
L
H
H
L
T
L
H
H
L
L
L
L
L
L
H
H
L
X
X
H
H
PIN NAMES
L
H
EN
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Low Half-Word
Read
DQ(31:0)
E1
E2
HHWE
LWHE
Data Input/Output
Enable (Active Low)
Enable (Active High)
High half-word enable
Low half-word enable
G
V
DD1
V
DD2
V
S S
Output Enable
Power (1.8V)
Power (2.5V)
Ground
PM
A(16:0)
Address
W
Write Enable
DQ(31:16)
Data Out
DQ(15:0)
3-State
DQ(31:16)
Data Out
DQ(15:0)
Data Out
DQ(31:16)
Data In
DQ(15:0)
Data In
DQ(31:16)
3-State
DQ(15:0)
Data In
DQ(31:16)
Data In
DQ(15:0)
3-State
DQ(31:16)
DQ(15:0)
All 3-State
DQ(31:16)
DQ(15:0)
All 3-State
High Half-Word
Read
L
H
Word Read
EL
O
X
L
Word Write
X
L
Low Half-Word
Write
EV
X
L
High Half-Word
Write
D
H
H
3-State
X
X
3-State
IN
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
2
READ CYCLE
A combination of W and E2 greater than V
IH
(min) and E1
less than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or
valid address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while the chip is
enabled with G asserted and W deasserted. Valid data appears
on data outputs DQ(31:0) after the specified t
AVQV
is
satisfied. Outputs remain active throughout the entire cycle.
As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum
read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by the latter of E1 and E2 going active
while G remains asserted, W remains deasserted, and the
addresses remain stable for the entire cycle. After the
specified t
ETQV
is satisfied, the 32-bit word addressed by
A(16:0) is accessed and appears at the data outputs DQ(31:0).
SRAM Read Cycle 3, the Output Enable-controlled Access
in Figure 3c, is initiated by G going active while E1 and E2
are asserted, W is deasserted, and the addresses are stable.
Read access time is t
GLQV
unless t
AVQV
or t
ETQV
have not
been satisfied.
high-impedance state by G, the user must wait t
WLQZ
before
applying data to the sixteen bidirectional pins DQ(31:0) to
avoid bus contention.
WORD ENABLES
Separate byte enable controls (LHWE and HHWE) allow
individual bytes to be accessed. LHWE controls the lower
bits DQ(15:0). HHWE controls the upper bits DQ(31:16).
Writing to the device is performed by asserting E1, E2 and
the byte enables. Reading the device is performed by
asserting E1, E2, G, and the byte enables while W is held
inactive (HIGH).
HHWE
0
0
LHWE
0
1
OPERATION
32-bit read or write cycle
16-bit high half-word read or write
cycle (low byte bi-direction pins
DQ(15:0) are in 3 -state)
32-bit low half-word read or write
cycle (high half word bi-direction
pins DQ(31:16) are in 3 -state)
High and Low byte bi-directional
pins remain in 3-state, write function
disabled
1
0
Write Cycle
A combination of W and E1 less than V
IL
(max) and E2
greater than V
IH
(min) defines a write cycle. The state of G is
a “don’t care” for a write cycle. The outputs are placed in the
high-impedance state when eitherG is greater than V
IH
(min),
or when W is less than V
IL
(max).
RADIATION HARDNESS
EL
O
3
The UT8R128K32 SRAM incorporates special design,
layout, and process features which allows operation in a
limited radiation environment.
Table 2. Radiation Hardness Design Specifications
1
100K
1.0E-10
rad(Si)
Errors/Bit-Day
IN
Write Cycle 1, the Write Enable-controlled Access in Figure
4a, is defined by a write terminated by W going high, with
E1 and E2 still active. The write pulse width is defined by
t
WLWH
when the write is initiated by W, and by t
ETWH
when
the write is initiated by E1 or E2. Unless the outputs have
been previously placed in the high-impedance state byG, the
user must wait user must wait t
WLQZ
before applying data to
the 32 bidirectional pins DQ(15:0) to avoid bus contention.
EV
Notes:
1. The SRAM is immune to latchup to particles of 128MeV-cm
2
/mg.
2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils
of Aluminum.
D
Supply Sequencing
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
Write Cycle 2, the Chip Enable-controlled Access in Figure
4b, is defined by a write terminated by the latter of E1 or E2
going inactive. The write pulse width is defined by t
WLEF
when the write is initiated byW, and by t
ETEF
when the write
is initiated by either E1or E2 going active. For the W initiated
write, unless the outputs have been previously placed in the
PM
EN
1
1
Total Dose
Heavy Ion
Error Rate
2
T
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
Thermal resistance, junction-to-case
2
DC input current
LIMITS
-0.3 to 2.0V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
1.2W
+150°C
5°C/W
±
5 mA
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD1
V
DD2
T
C
V
IN
PARAMETER
Positive supply voltage
Positive supply voltage
Case temperature range
DC input voltage
EL
O
4
IN
D
EV
PM
EN
T
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Test per MIL-STD-883, Method 1012.
LIMITS
1.7 to 1.9V
2.25 to 3.6V
-55 to +125°C
0V to V
DD2
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(-55°C to +125°C)
SYMBOL
V
IH
V
IL
V
OL1
V
OH1
C
IN 1
C
IO 1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
I
OL
= 8mA,V
DD2
=V
DD2
(min)
I
OH
= -4mA,V
DD2
=V
DD2
(min)
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
IN
= V
DD2
and V
SS
V
O
= V
DD2
and V
SS
V
DD2
= V
DD2
(max), G = V
DD2
(max)
I
OS 2, 3
Short-circuit output current
V
DD2
= V
DD2
(max), V
O
= V
DD2
V
DD2
= V
DD2
(max), V
O
= V
SS
I
DD1
(OP
1
)
Supply current operating
@ 1MHz
Inputs : V
IL
= V
SS
+ 0.2V,
-100
+100
mA
-2
-2
.8*V
DD2
7
7
2
2
CONDITION
MIN
.7*V
DD2
.3*V
DD2
.2*V
DD2
MAX
UNIT
V
V
V
V
pF
pF
µA
µA
PM
EN
5
T
1
mA
105
mA
7
mA
460
mA
1
mA
5
mA
V
IH
= V
DD2
+ 0.2V , I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
I
DD1
(OP
2
)
Supply current operating
@100MHz,
Inputs : V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD2
+ 0.2V, I
OUT
= 0
V
DD1
= V
DD1
(max), V
DD2
= V
DD2
(max)
I
DD2
(OP
1
)
Supply current operating
@ 1MHz
D
I
DD
(SB)
4
Supply current standby
@0Hz
I
DD
(SB)
4
Total Supply current standby
A(16:0) @ 100MHz
IN
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
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