P4C1281/P4C1282
ULTRA HIGH SPEED 64K X 4
cmoS STATIc RAmS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Industrial)
– 20/25/35/45 ns (Military)
Low Power Operation
5V ± 10% Power Supply
Separate Inputs and Outputs
– P4C1281 Input Data at Outputs during Write
– P4C1282 Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
DESCRIPTIOn
The P4C1281 and P4C1282 are 262,144-bit (64Kx4) ultra
high-speed static RAMs similar to the P4C1258, but with
separate data I/O pins. The P4C1281 features a transpar-
ent write operation; the outputs of the P4C1282 are in high
impedance during the write cycle. The RAMs operate from
a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
The P4C1281 and P4C1282 are available in 28-pin 300
mil DIP and SOJ, and a 28-pin 350x550 mil LCC providing
excellent board level densities.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (P5, C5, D5-2), SOJ (J5)
LCC (L5)
Document #
SRAM136
REV OR
Revised July 2009
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
MAxIMUM RATIngS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7
-0.5 to VCC + 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATIng COnDITIOnS
grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
gnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
8
10
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
P4C1281/1282
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
V
CC
= Min, I
IN
= -18 mA
I
OL
= +8 mA, V
CC
= Min
I
OH
= -4 mA, V
CC
= Min
V
CC
= Max,
V
IN
= GND to V
CC
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
Unit
V
V
V
V
V
V
V
2.4
-10
-5
-10
-5
—
—
—
—
+10
Input Leakage Current
µA
+5
+10
µA
+5
40
mA
35
20
mA
15
I
LO
Output Leakage Current
V
CC
= Max,
CE
= V
IH
,
V
OUT
= GND to V
CC
I
SB
Standby Power Supply Current
(TTL Input Levels)
CE
≥ V
IH
, V
CC
= Max, f = Max,
Outputs Open
CE
≥ V
HC
, V
CC
= Max, f = 0,
Outputs Open
V
IN
≤ V
LC
or V
IN
≥ V
HC
I
SB1
Standby Power Supply Current
(CMOS Input Levels)
N/A = Not applicable
Document #
SRAM136
REV OR
Page 2
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Sym
I
CC
Parameter
Dynamic Operating Current*
Temperature Range
Commercial
Industrial
Military
-12
170
N/A
N/A
-15
160
170
N/A
-20
155
160
160
-25
150
155
155
-35
N/A
150
150
-45
N/A
N/A
145
Unit
mA
mA
mA
* V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Chip Enable to Power Up Time
Chip Disable to Power Down
0
12
2
2
7
0
15
-12
Min
12
12
12
2
2
8
0
20
Max
-15
Min
15
15
15
2
2
10
0
25
Max
-20
Min
20
20
20
2
2
10
0
25
Max
-25
Min
25
25
25
2
2
15
0
30
Max
-35
Min
35
35
35
2
2
15
Max
-45
Min
45
45
45
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF READ CYCLE nO. 1 (ADDRESS COnTROLLED)
(5,6)
TIMIng WAVEFORM OF READ CYCLE nO. 2 (CE COnTROLLED)
(5,7,8)
Document #
SRAM136
REV OR
Page 3
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym Parameter
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
AWE
t
ADV
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Address Hold Time from End of
Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
Write Enable to Data-out Valid
(P4C1281)
Data-in Valid to Data-out Valid
(P4C1281)
2
12
12
-12
Min
12
8
8
0
9
0
6
0
6
2
13
13
Max
13
10
10
0
10
0
7
0
7
2
18
18
-15
Min
Max
15
15
15
0
15
0
10
0
8
2
20
20
-20
Min
Max
20
20
20
0
20
0
13
0
10
2
30
30
-25
Min
Max
30
30
25
0
25
0
15
0
10
2
35
35
-35
Min
Max
40
35
35
0
35
0
20
0
15
-45
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition
LOW.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
9. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
Document #
SRAM136
REV OR
Page 4
P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(10, 11, 12)
TIMIng WAVEFORM OF WRITE CYCLE nO. 2 (CE COnTROLLED)
(10, 11, 12)
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM136
REV OR
Page 5
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