EPM7256BTI144-5 datasheet, PDF

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EPM7256BTI144-5: DescriptionEE PLD, 5ns, 256-Cell, CMOS, PQFP144, TQFP-144; CategoryProgrammable logic devices Programmable logic; File Size3MB，147 Pages; ManufacturerAltera (Intel)

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EPM7256BTI144-5 Overview

EE PLD, 5ns, 256-Cell, CMOS, PQFP144, TQFP-144

EPM7256BTI144-5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	QFP
package instruction	LFQFP, QFP144,.63SQ,20
Contacts	144
Reach Compliance Code	compliant
Other features	YES
maximum clock frequency	188.7 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G144
JESD-609 code	e0
JTAG BST	YES
length	20 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	120
Number of macro cells	256
Number of terminals	144
organize	0 DEDICATED INPUTS, 120 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP144,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	220
power supply	1.8/3.3,2.5 V
Programmable logic type	EE PLD
propagation delay	5 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	20 mm

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MAX 7000B

Programmable Logic

Device Family

Data Sheet

October 2000, ver. 2.1

Features...

Preliminary

Information

High-performance 2.5-V CMOS EEPROM-based programmable

logic devices (PLDs) built on second-generation Multiple Array

MatriX (MAX

) architecture (see

Table 1)

– Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V

MAX 7000A device families

– High-density PLDs ranging from 600 to 10,000 usable gates

–

3.5-ns pin-to-pin logic delays with counter frequencies in excess

of 285.7 MHz

Advanced 2.5-V in-system programmability (ISP)

–

Programs through the built-in IEEE Std. 1149.1 Joint Test Action

Group (JTAG) interface with advanced pin-locking capability

–

Enhanced ISP algorithm for faster programming

–

ISP_Done bit to ensure complete programming

–

Pull-up resistor on I/O pins during in-system programming

–

ISP circuitry compliant with IEEE Std. 1532

For information on in-system programmable 5.0-V MAX 7000S or 3.3-V

MAX 7000A devices, see the

MAX 7000 Programmable Logic Device Family

Data Sheet

or the

MAX 7000A Programmable Logic Device Family Data Sheet.

Note (1)

EPM7064B

1,250

3.5

2.3

1.0

2.3

285.7

Table 1. MAX 7000B Device Features

Feature

Usable gates

Macrocells

Logic array blocks

Maximum user I/O

pins

(ns)

FSU

(ns)

CO1

(ns)

CNT

(MHz)

Note:

(1)

EPM7032B

600

3.5

2.3

1.0

2.3

285.7

EPM7128B

2,500

128

100

4.0

2.8

1.0

2.8

238.1

EPM7256B

5,000

256

164

5.0

3.5

1.0

3.5

188.7

EPM7512B

10,000

512

212

6.0

3.9

1.0

3.7

163.9

Contact Altera for up-to-date information on timing information.

Altera Corporation

A-DS-MAX7000B-02.1

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