K4F170811D, K4F160811D
K4F170812D, K4F160812D
CMOS DRAM
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power con-
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Part Identification
- K4F170811D-B(F) (5V, 4K Ref.)
- K4F160811D-B(F) (5V, 2K Ref.)
- K4F170812D-B(F) (3.3V, 4K Ref.)
- K4F160812D-B(F) (3.3V, 2K Ref.)
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
Unit : mW
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
2K
605
550
• Single +3.3V±0.3V power supply (3.3V product)
•
Active Power Dissipation
3.3V
4K
-50
-60
324
288
2K
396
360
4K
495
440
5V
Speed
FUNCTIONAL BLOCK DIAGRAM
•
Refresh Cycles
Part
NO.
K4F170811D
K4F170812D
K4F160811D
K4F160812D
V
CC
5V
3.3V
5V
3.3V
2K
32ms
Refresh Control
Refresh Counter
Memory Array
2,097,152 x 8
Cells
Refresh Refresh period
cycle
Normal
L-ver
4K
64ms
128ms
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Data in
Refresh Timer
Row Decoder
Sense Amps & I/O
Buffer
•
Performance Range
Speed
-50
-60
DQ0
to
DQ7
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
PC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
A0-A11
(A0 - A10)
*1
A0 - A8
(A0 - A9)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Data out
Buffer
OE
Note)
*1
: 2K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
K4F170811D, K4F160811D
K4F170812D, K4F160812D
CMOS DRAM
PIN CONFIGURATION
(Top Views)
• K4F17(6)0811(2)D-B
• K4F17(6)0811(2)D-F
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
*A11 is N.C for K160811(2)D(5V/3.3V,
2K Ref.
product)
B : 300mil 28 SOJ
F : 300mil 28 TSOP II
Pin Name
A0 - A11
A0 - A10
DQ0 - 7
V
SS
RAS
CAS
W
OE
V
CC
N.C
Pin Function
Address Inputs (4K Product)
Address Inputs (2K Product)
Data In/Out
Ground
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5V)
Power(+3.3V)
No Connection (2K Ref. product)
K4F170811D, K4F160811D
K4F170812D, K4F160812D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
3.3V
V
IN,
V
OUT
V
CC
Tstg
P
D
I
OS
Address
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
50
Rating
5V
CMOS DRAM
Units
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
50
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
Min
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
-0.3
*2
3.3V
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
*1
0.8
Min
4.5
0
2.4
-1.0
*2
5V
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1.0
*1
0.8
V
V
V
V
Units
*1 : V
CC
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
CC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.3V,
all other input pins not under test=0 Volt)
3.3V
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-2mA)
Output Low Voltage Level(I
OL
=2mA)
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.5V,
all other input pins not under test=0 Volt)
5V
Output Leakage Current
(Data out is disabled, 0V≤V
OUT
≤V
CC
)
Output High Voltage Level(I
OH
=-5mA)
Output Low Voltage Level(I
OL
=4.2mA)
Symbol
I
I(L)
I
O(L)
V
OH
V
OL
I
I(L)
I
O(L)
V
OH
V
OL
Min
-5
-5
2.4
-
-5
-5
2.4
-
Max
5
5
-
0.4
5
5
-
0.4
Units
uA
uA
V
V
uA
uA
V
V
K4F170811D, K4F160811D
K4F170812D, K4F160812D
DC AND OPERATING CHARACTERISTICS
(Continued)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
CC7
I
CCS
Power
Don′t care
Normal
L
Don′t care
Don′t care
Normal
L
Don′t care
L
L
Speed
-50
-60
Don′t care
-50
-60
-50
-60
Don′t care
-50
-60
Don′t care
Don′t care
Max
K4F170812D
90
80
1
1
90
80
80
70
0.5
200
90
80
250
200
K4F160812D
110
100
1
1
110
100
90
80
0.5
200
110
100
250
200
K4F170811D
90
80
2
1
90
80
80
70
1
250
90
80
300
250
CMOS DRAM
K4F160811D
110
100
2
1
110
100
90
80
1
250
110
100
300
250
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
mA
mA
uA
uA
I
CC1
* : Operating Current (RAS and CAS cycling @t
RC
=min.)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
* : RAS-only Refresh Current (CAS=V
IH
, RAS cycling @t
RC
=min.)
I
CC4
* : Fast Page Mode Current (RAS=V
IL
, CAS, Address cycling @t
PC
=min.)
I
CC5
: Standby Current (RAS=CAS=W=V
CC
-0.2V)
I
CC6
* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @t
RC
=min.)
I
CC7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
CC
-0.2V, Input low voltage(V
IL
)=0.2V, CAS=0.2V,
DQ=Don′t care, T
RC
=31.25us(4K/L-ver), 62.5us(2K/L-ver),
T
RAS
=T
RAS
min~300ns
I
CCS
: Self Refresh Current
RAS=CAS=V
IL
, W=OE=A0 ~ A11=V
CC
-0.2V or 0.2V,
DQ0 ~ DQ7=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
CC3
and I
CC6
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one fast page mode cycle time, t
PC
.
K4F170811D, K4F160811D
K4F170812D, K4F160812D
CAPACITANCE
(T
A
=25°C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ7]
Symbol
C
IN1
C
IN2
C
DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
See note 1,2)
Test condition (5V device) : V
CC
=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Test condition (3.3V device) : V
CC
=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Symbol
Min
-50
Max
Min
110
155
50
13
25
0
0
3
30
50
13
50
13
20
15
5
0
10
0
10
25
0
0
0
10
10
13
13
10K
37
25
10K
13
50
0
0
3
40
60
15
60
15
20
15
5
0
10
0
10
30
0
0
0
10
10
15
15
10K
45
30
10K
15
50
60
15
30
-60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
4
10
3,4,10
3,4,5
3,10
3
6
2
Units
Notes
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
90
133
FPGA/CPLD
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