16 x 16 PARALLEL
CMOS MULTIPLIERS
Integrated Device Technology, Inc.
IDT7216L
IDT7217L
FEATURES:
•
•
•
•
•
•
16 x 16 parallel multiplier with double precision product
16ns clocked multiply time
Low power consumption: 120mA
Produced with advanced submicron CMOS high perfor-
mance technology
IDT7216L is pin- and function compatible with TRW
MPY016H/K and AMD Am29516
IDT7217L requires a single clock with register enables
making it pin- and function compatible with AMD
Am29517
Configured for easy array expansion
User-controlled option for transparent output register
mode
Round control for rounding the MSP
Input and output directly TTL-compatible
Three-state output
Available in Top Braze, DIP, PLCC, Flatpack and Pin
Grid Array
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-86873 is listed on this
function for IDT7216 and Standard Military Drawing
#5962-87686 is listed for this function for IDT7217.
Speeds available: Commercial: L16/20/25/35/45/55/65
Military:
L20/25/30/40/55/65/75
IDT7216
RND
Y
M
Y
15-0
/P
15-0
16
REGISTER
YREGISTER
DESCRIPTION:
The IDT7216/IDT7217 are high-speed, low-power
16 x 16-bit multipliers ideal for fast, real time digital signal
processing applications. Utilization of a modified Booths
algorithm and IDT’s high-performance, submicron CMOS
technology, has achieved speeds comparable to bipolar (20ns
max.), at 1/10 the power consumption.
The IDT7216/IDT7217 are ideal for applications requiring
high-speed multiplication such as fast Fourier transform
analysis, digital filtering, graphic display systems, speech
synthesis and recognition and in any system requirement
where multiplication speeds of a mini/microcomputer are
inadequate.
All input registers, as well as LSP and MSP output regis-
ters, use the same positive edge-triggered D-type flip-flop. In
the IDT7216, there are independent clocks (CLKX, CLKY,
CLKM, CLKL) associated with each of these registers. The
IDT7217 has only a single clock input (CLK) and three register
enables.
ENX
and
ENY
control the two input registers, while
ENP
controls the entire product.
The IDT7216/IDT7217 offer additional flexibility with the FA
control and
MSPSEL
functions. The FA control formats the
output for two’s complement by shifting the MSP up one bit
and then repeating the sign bit in the MSB of the LSP. The
•
•
•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAMS
X
M
X
15-0
16
XREGISTER
X
M
IDT7217
X
15-0
RND
16
REGISTER
Y
M
Y
15-0
/P
15-0
16
YREGISTER
XREGISTER
CLKY
CLKX
OEL
CLK
ENX
ENY
MULTIPLIER
ARRAY
MULTIPLIER
ARRAY
OEL
FA
FT
CLKM
CLKL
MSPSEL
OEP
FORMAT ADJUST
MSP
LSP
REGISTER REGISTER
16
16
FA
FT
ENP
FORMAT ADJUST
MSP
LSP
REGISTER REGISTER
16
16
MULTIPLEXER
MSPSEL
OEP
MULTIPLEXER
PRODUCT
16
2580 drw 01
PRODUCT
16
2580 drw 02
MSP
OUT
(P
31
- P
16
)
The IDT Logo is a registered trademark of Integrated Device Technology, Inc.
MSP
OUT
(P
31
- P
16
)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
AUGUST 1995
DSC-2023/6
11.3
1
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Cont’d.)
MSPSEL
low selects the MSP to be available at the product
output port, while a high selects the LSP to be available.
Keeping this pin low will ensure compatibility with the TRW
MPY016H.
The IDT7216/IDT7217 multipliers are manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to applications demanding the
highest level of performance and reliability.
PIN CONFIGURATIONS
IDT7216
IDT7217
X
4
X
3
X
2
X
1
X
0
OEL
CLKL
CLKY
P
0
, Y
0
P
1
, Y
1
P
2
, Y
2
P
3
, Y
3
P
4
, Y
4
P
5
, Y
5
P
6
, Y
6
P
7
, Y
7
P
8
, Y
8
P
9
, Y
9
P
10
, Y
10
P
11
, Y
11
P
12
, Y
12
P
13
, Y
13
P
14
, Y
14
P
15
, Y
15
P
0
, P
16
P
1
, P
17
P
2
, P
18
P
3
, P
19
P
4
, P
20
P
5
, P
21
P
6
, P
22
P
7
, P
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
C64-2 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
X
5
X
6
X
7
X
8
X
9
X
10
X
11
X
12
X
13
X
14
X
15
CLKX
RND
X
M
Y
M
V
CC
V
CC
GND
GND
MSPSEL
FT
FA
OEP
CLKM
P
15
, P
31
P
14
, P
30
P
13
, P
29
P
12
, P
28
P
11
, P
27
P
10
, P
26
P
9
, P
25
P
8
, P
24
2580 drw 03
X
4
X
3
X
2
X
1
X
0
OEL
CLK
ENY
P
0
, Y
0
P
1
, Y
1
P
2
, Y
2
P
3
, Y
3
P
4
, Y
4
P
5
, Y
5
P
6
, Y
6
P
7
, Y
7
P
8
, Y
8
P
9
, Y
9
P
10
, Y
10
P
11
, Y
11
P
12
, Y
12
P
13
, Y
13
P
14
, Y
14
P
15
, Y
15
P
0
, P
16
P
1
, P
17
P
2
, P
18
P
3
, P
19
P
4
, P
20
P
5
, P
21
P
6
, P
22
P
7
, P
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
C64-2 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
X
5
X
6
X
7
X
8
X
9
X
10
X
11
X
12
X
13
X
14
X
15
ENX
RND
X
M
Y
M
V
CC
V
CC
GND
GND
MSPSEL
FT
FA
OEP
ENP
P
15
, P
31
P
14
, P
30
P
13
, P
29
P
12
, P
28
P
11
, P
27
P
10
, P
26
P
9
, P
25
P
8
, P
24
2580 drw 04
64-PIN DIP
TOP VIEW
64-PIN DIP
TOP VIEW
11.3
2
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont’d.)
IDT7216/IDT7217
11
10
09
08
07
06
05
04
03
02
01
Pin 1
Designator
A
X
11
X
9
X
7
X
5
X
3
X
1
OEL
CLKY
or
ENY*
NC
X
12
X
10
X
8
X
6
X
4
X
2
X
0
CLKL
or
CLK*
X
13
X
14
X
15
CLKX
or
ENX*
RND
X
M
Y
M
V
CC
GND
FT
FA
OEP
CLKM
or
ENP*
V
CC
GND MSP-
SEL
NC
P
31,
P
15
P
29,
P
13
P
27,
P
11
P
25,
P
9
P
23,
P
7
P
21,
P
5
P
19,
P
3
P
17,
P
1
P
30,
P
14
P
28,
P
12
P
26,
P
10
G68-2
P
24,
P
8
P
22,
P
6
P
20,
P
4
P
18,
P
2
Y
2,
P
2
Y
3,
P
3
C
Y
4,
P
4
Y
5,
P
5
D
Y
6,
P
6
Y
7,
P
7
E
Y
8,
P
8
Y
9,
P
9
F
Y
10,
P
10
Y
11,
P
11
G
Y
12,
P
12
Y
13,
P
13
H
Y
14,
P
14
Y
15,
P
15
J
P
16,
P
0
NC
K
NC
Y
0,
P
0
Y
1,
P
1
B
L
*Pin designation for IDT7217
PGA
TOP VIEW
2580 drw 05
11.3
3
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont’d.)
IDT7216
OEP
FA
FT
MSPSEL
GND
GND
V
CC
V
CC
Y
M
X
M
RND
CLKX
X
15
X
14
X
13
IDT7217
ENP
OEP
FA
FT
MSPSEL
GND
GND
V
CC
V
CC
Y
M
X
M
RND
ENX
X
15
X
14
X
13
64636261 605958575655 545352 515049
64636261 605958575655 545352 515049
P
15
,
P
31
P
14
,
P
30
P
13
,
P
29
P
12
,
P
28
P
11
,
P
27
P
10
,
P
26
P
9
,
P
25
P
8
,
P
24
P
7
,
P
23
P
6
,
P
22
P
5
,
P
21
P
4
,
P
20
P
3
,
P
19
P
2
,
P
18
P
1
,
P
17
P
0
,
P
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
F64-1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
OEL
CLKL
CLKY
P
15
,
P
14
,
P
13
,
P
12
,
P
11
,
P
10
,
P
9
,
P
8
,
P
7
,
P
6
,
P
5
,
P
4
,
P
3
,
P
2
,
P
1
,
P
0
,
P
31
P
30
P
29
P
28
P
27
P
26
P
25
P
24
P
23
P
22
P
21
P
20
P
19
P
18
P
17
P
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
F64-1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
OEL
CLK
ENY
17181920 212223242526 272829 303132
17181920 212223242526 272829 303132
P
15
,
Y
15
P
14
,
Y
14
P
13
,
Y
13
P
12
,
Y
12
P
11
,
Y
11
P
10
,
Y
10
P
9
,
Y
9
P
8
,
Y
8
P
7
,
Y
7
P
6
,
Y
6
P
5
,
Y
5
P
4
,
Y
4
P
3
,
Y
3
P
2
,
Y
2
P
1
,
Y
1
P
0
,
Y
0
2580 drw 06
P
15
,
Y
15
P
14
,
Y
14
P
13
,
Y
13
P
12
,
Y
12
P
11
,
Y
11
P
10
,
Y
10
P
9
,
Y
9
P
8
,
Y
8
P
7
,
Y
7
P
6
,
Y
6
P
5
,
Y
5
P
4
,
Y
4
P
3
,
Y
3
P
2
,
Y
2
P
1
,
Y
1
P
0
,
Y
0
2580 drw 07
64-LEAD FLATPACK
TOP VIEW
64-LEAD FLATPACK
TOP VIEW
NC
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
OEL
CLKL
CLKY
60 59 58 5756 5554 53 5251 50 4948 47 46 45 44
60 59 58 5756 5554 53 5251 50 4948 47 46 45 44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
X
13 61
X
14 62
X
15 63
CLKX
64
RND
65
X
M 66
Y
M 67
V
CC 68
V
CC 1
GND
2
GND
3
MSPSEL
4
FT
5
FA
6
OEP
7
CLKM
8
NC
9
J68-1
L68-1, L68-1
NC
P
0
, Y
0
P
1
, Y
1
P
2
, Y
2
P
3
, Y
3
P
4
, Y
4
P
5
, Y
5
P
6
, Y
6
P
7
, Y
7
P
8
, Y
8
P
9
, Y
9
P
10
, Y
10
P
11
, Y
11
P
12
, Y
12
P
13
, Y
13
P
14
, Y
14
P
15
, Y
15
X
13 61
X
14 62
X
15 63
ENX
64
RND
65
X
M 66
Y
M 67
V
CC68
V
CC 1
GND
2
GND
3
MSPSEL
4
FT
5
FA
6
OEP
7
ENP
8
NC
9
NC
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
OEL
CLK
ENY
IDT7216
IDT7217
L68-1, L68-1
J68-1
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
P
0
, Y
0
P
1
, Y
1
P
2
, Y
2
P
3
, Y
3
P
4
, Y
4
P
5
, Y
5
P
6
, Y
6
P
7
, Y
7
P
8
, Y
8
P
9
, Y
9
P
10
, Y
10
P
11
, Y
11
P
12
, Y
12
P
13
, Y
13
P
14
, Y
14
P
15
, Y
15
10 1112 13 14 1516 17 1819 20 212223 24 25 26
P
15
, P
31
P
14
, P
30
P
13
, P
29
P
12
, P
28
P
11
, P
27
P
10
, P
26
P
9
, P
25
P
8
, P
24
P
7
, P
23
P
6
, P
22
P
5
, P
21
P
4
, P
20
P
3
, P
19
P
2
, P
18
P
1
, P
17
P
0
, P
16
NC
10 1112 13 14 1516 17 1819 20 2122 23 24 25 26
P
15
, P
31
P
14
, P
30
P
13
, P
29
P
12
, P
28
P
11
, P
27
P
10
, P
26
P
9
, P
25
P
8
, P
24
P
7
, P
23
P
6
, P
22
P
5
, P
21
P
4
, P
20
P
3
, P
19
P
2
, P
18
P
1
, P
17
P
0
, P
16
NC
2580 drw 08
2580 drw 09
PLCC
TOP VIEW
PLCC
TOP VIEW
11.3
4
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name
X
0
- X
15
Y
0 -
Y
15
/
P
0
- P
15
P
16
- P
31
I/O
I
I/O
O
I
I
I
I
Data Inputs
Y
0 -
Y
15
are data inputs
P
0
- P
15
are LSP register output, enabled when
OEL
= 0
Data Output (LSP or MSP)
Output enable control for LSP (least significant product). When low enables P
0
- P
15
. When high P
0
- P
15
tristated.
Output enable control for MSP (most significant product). When low enables P
16
- P
31.
When high P
16
-
P
31
tristated.
Mode control for each data word. Low designates unsigned data input and high designates two's
complement.
"Round" control for rounding of MSP. When high, 1 is added to the most significant bit of LSP. This
signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2
-15
bit (P
15
). When
RND = 1 and FA = 0, 1 is added to the 2
-16
bit (P
14
). The RND input is registered. It is clocked on the
rising edge of the logical OR of CLKX and CLKY in the 7216 and on the rising edge of CLK in the 7217.
Rounding always occurs in the positive direction which may introduce a systematic bias.
When low, MSP is output on P
16
- P
31
lines. When high, LSP is output on P
16
- P
31.
Format adjust control. When high, a full 32 bit product is selected. When low, a left shifted 31 bit product
is selected with the sign bit replicated in the LSP. FA is normally high, except for certain fractional two's
complement applications (see multiplier input / output formats).
Flow through control. When high, both MSP and LSP registers are by-passed.
7217 X, Y, RND, LSP and MSP register clock input.
7216 X register clock input. Also clocks RND register.
7216 Y register clock input. Also clocks RND register.
7216 LSP register clock input.
7216 MSP register clock input.
7217 X register clock enable. Also enables RND register clock.
7217 Y register clock enable. Also enables RND register clock.
Description
OEL
OEP
X
M,
Y
M
RND
MSPSEL
FA
I
I
FT
CLK
CLKX
CLKY
CLKL
CLKM
I
I
I
I
I
I
I
I
ENX
ENY
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
TERM
Rating
Power Supply
Voltage
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
V
CC
+ 0.5
Military
–0.5 to +7.0
V
CC
+ 0.5
Unit
V
V
°C
°C
°C
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
NOTE:
2580 tbl 04
1. This parameter is measured at characterization and not tested.
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
–55 to +125
–65 to +135
–65 to +150
50
NOTE:
2580 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
11.3
5
EL
京公网安备 11010802033920号
EEWORLD
