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SIHFPS40N60K-E3

Description
TRANSISTOR 40 A, 600 V, 0.13 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, SUPER-247, 3 PIN, FET General Purpose Power
CategoryDiscrete semiconductor    The transistor   
File Size180KB,9 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance
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SIHFPS40N60K-E3 Overview

TRANSISTOR 40 A, 600 V, 0.13 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, SUPER-247, 3 PIN, FET General Purpose Power

SIHFPS40N60K-E3 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerVishay
package instructionIN-LINE, R-PSIP-T3
Contacts3
Reach Compliance Codeunknown
Avalanche Energy Efficiency Rating (Eas)600 mJ
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage600 V
Maximum drain current (Abs) (ID)40 A
Maximum drain current (ID)40 A
Maximum drain-source on-resistance0.13 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PSIP-T3
JESD-609 codee3
Humidity sensitivity level1
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)570 W
Maximum pulsed drain current (IDM)160 A
Certification statusNot Qualified
surface mountNO
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON

SIHFPS40N60K-E3 Preview

IRFPS40N60K, SiHFPS40N60K
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
V
DS
(V)
R
DS(on)
()
Q
g
(Max.) (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
330
84
150
Single
D
FEATURES
600
0.110
• Low Gate Charge Q
g
Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Available
RoHS*
COMPLIANT
• Fully Characterized Capacitance and Avalanche Voltage
and Current
• Enhanced Body Diode dV/dt Capability
• Compliant to RoHS Directive 2002/95/EC
Super-247
G
S
D
G
S
N-Channel MOSFET
APPLICATIONS
• Hard Switching Primary or PFC Switch
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
• Motor Drive
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
Super-247
IRFPS40N60KPbF
SiHFPS40N60K-E3
IRFPS40N60K
SiHFPS40N60K
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
a
Linear Derating Factor
Single Pulse Avalanche Energy
b
Repetitive Avalanche
Current
a
T
C
= 25 °C
Repetitive Avalanche Energy
a
Maximum Power Dissipation
Peak Diode Recovery dV/dt
c
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
E
AS
I
AR
E
AR
P
D
dV/dt
T
J
, T
stg
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
LIMIT
600
± 30
40
24
160
4.5
600
40
57
570
7.5
- 55 to + 150
300
d
W/°C
mJ
A
mJ
W
V/ns
°C
A
UNIT
V
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting T
J
= 25 °C, L = 0.84 mH, R
g
= 25
,
I
AS
= 38 A, dV/dt = 5.5 V/ns (see fig. 12a).
c. I
SD
38 A, dI/dt
150 A/μs, V
DD
V
DS
, T
J
150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91261
S11-0112-Rev. B, 31-Jan-11
www.vishay.com
1
IRFPS40N60K, SiHFPS40N60K
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
SYMBOL
R
thJA
R
thCS
R
thJC
TYP.
-
0.24
-
MAX.
40
-
0.22
UNIT
°C/W
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Effective Output Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Body Diode Recovery Current
Forward Turn-On Time
Current
a
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
C
oss
C
oss
eff.
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 30 V
V
DS
= 600 V, V
GS
= 0 V
V
DS
= 480 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 24 A
b
A
b
V
DS
= 50 V, I
D
= 24
600
-
3.0
-
-
-
-
21
-
-
-
-
-
-
-
-
-
-
-
0.63
-
-
-
-
0.110
-
7970
750
75
9440
200
260
-
-
-
47
110
97
60
-
-
5.0
± 100
50
250
0.130
-
-
-
-
-
-
-
330
84
150
-
-
-
-
V
V/°C
V
nA
μA
S
V
GS
= 0 V,
V
DS
= 25 V,
f = 1.0 MHz, see fig. 5
V
DS
= 1.0 V , f = 1.0 MHz
V
GS
= 0 V
V
DS
= 480 V , f = 1.0 MHz
V
DS
= 0 V to 480 V
c
I
D
= 38 A, V
DS
= 480 V,
see fig. 6 and 13
b
V
GS
= 10 V
V
DD
= 300 V, I
D
= 38 A,
R
G
= 4.3
,
see fig. 10
b
pF
nC
-
-
-
ns
-
-
-
-
-
-
-
-
-
-
-
630
730
14
17
39
40
A
160
1.5
950
1090
20
25
58
V
ns
μC
A
G
S
T
J
= 25 °C, I
S
= 38 A, V
GS
= 0 V
b
T
J
= 25 °C
T
J
= 125 °C
T
J
= 25 °C
T
J
= 125 °C
T
J
= 25 °C
I
F
= 38 A, dI/dt = 100
A/μs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
and L
D
)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width
300 μs; duty cycle
2 %.
c. C
oss
eff. is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DS
.
www.vishay.com
2
Document Number: 91261
S11-0112-Rev. B, 31-Jan-11
IRFPS40N60K, SiHFPS40N60K
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1000
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1000
ID, Drain-to-Source Current (A)
100
100
T
J
= 150
°
C
10
I
D
, Drain-to-Source Current (A)
10
1
1
T
J
= 25
°
C
0.1
4.5V
0.01
0.1
20μs PULSE WIDTH
Tj = 25°C
0.001
0.1
1
10
100
0.01
4
6
8
10
V DS= 50V
20μs PULSE WIDTH
11
13
15
VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
V
GS
Gate-to-Source Voltage (V)
,
Fig. 3 - Typical Transfer Characteristics
100
ID, Drain-to-Source Current (A)
R
DS(on)
, Drain-to-Source On Resistance
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
3.5
I
D
= 38A
3.0
2.5
(Normalized)
2.0
4.5V
1
1.5
1.0
20μs PULSE WIDTH
Tj = 150°C
0.1
0.1
1
10
100
0.5
V
GS
= 10V
0.0
-60
-40
-20
0
20
40
60
80
100
120
140
160
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
T
J
, Junction Temperature
(
°
C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91261
S11-0112-Rev. B, 31-Jan-11
www.vishay.com
3
IRFPS40N60K, SiHFPS40N60K
Vishay Siliconix
100000
VGS
C
iss
C
rss
C
oss
= 0V,
f = 1 MHZ
=C +C , C
SHORTED
gs
gd
ds
=C
gd
=C +C
ds
gd
1000
10000
C, Capacitance(pF)
Ciss
I
SD
, Reverse Drain Current (A)
100
1000
10
T
J
= 150
°
C
Coss
100
T
J
= 25
°
C
1
Crss
10
1
10
100
1000
V
GS
= 0 V
0.1
0.2
0.6
0.9
1.3
1.6
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
V
SD
,Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
12
I
D
=
38A
1000
V
DS
= 480V
V
DS
= 300V
V
DS
= 120V
OPERATION IN THIS AREA
LIMITED BY R DS(on)
10
V
GS
, Gate-to-Source Voltage (V)
7
ID, Drain-to-Source Current (A)
100
10
100μsec
1msec
5
1
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
1
10
100
1000
10000
2
0
0
50
100
150
200
250
0.1
Q
G
, Total Gate Charge (nC)
VDS , Drain-toSource Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
www.vishay.com
4
Document Number: 91261
S11-0112-Rev. B, 31-Jan-11
IRFPS40N60K, SiHFPS40N60K
Vishay Siliconix
R
D
40
V
DS
V
GS
R
G
D.U.T.
+
-
V
DD
10 V
30
I
D
, Drain Current (A)
Pulse width
1 µs
Duty factor
0.1 %
20
Fig. 10a - Switching Time Test Circuit
V
DS
90 %
10
0
25
50
75
100
125
150
T
C
, Case Temperature
( ° C)
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
1
(Z
thJC
)
D = 0.50
0.1
0.20
Thermal Response
0.10
0.05
0.01
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
DM
t
1
t
2
Notes:
1. Duty factor D =
2. Peak T
0.001
0.00001
0.0001
0.001
0.01
t
1
/ t
2
+T
C
1
J
= P
DM
x Z
thJC
0.1
t
1
, Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91261
S11-0112-Rev. B, 31-Jan-11
www.vishay.com
5

SIHFPS40N60K-E3 Related Products

SIHFPS40N60K-E3 SIHFPS40N60K
Description TRANSISTOR 40 A, 600 V, 0.13 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, SUPER-247, 3 PIN, FET General Purpose Power TRANSISTOR 40 A, 600 V, 0.13 ohm, N-CHANNEL, Si, POWER, MOSFET, SUPER-247, 3 PIN, FET General Purpose Power
Is it lead-free? Lead free Contains lead
Is it Rohs certified? conform to incompatible
Maker Vishay Vishay
package instruction IN-LINE, R-PSIP-T3 IN-LINE, R-PSIP-T3
Contacts 3 3
Reach Compliance Code unknown unknown
Avalanche Energy Efficiency Rating (Eas) 600 mJ 600 mJ
Shell connection DRAIN DRAIN
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 600 V 600 V
Maximum drain current (Abs) (ID) 40 A 40 A
Maximum drain current (ID) 40 A 40 A
Maximum drain-source on-resistance 0.13 Ω 0.13 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PSIP-T3 R-PSIP-T3
JESD-609 code e3 e0
Number of components 1 1
Number of terminals 3 3
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 150 °C 150 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR
Package form IN-LINE IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Polarity/channel type N-CHANNEL N-CHANNEL
Maximum power dissipation(Abs) 570 W 570 W
Maximum pulsed drain current (IDM) 160 A 160 A
Certification status Not Qualified Not Qualified
surface mount NO NO
Terminal surface Matte Tin (Sn) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE THROUGH-HOLE
Terminal location SINGLE SINGLE
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
transistor applications SWITCHING SWITCHING
Transistor component materials SILICON SILICON

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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