DSP56303VF100 datasheet, PDF - EEWORLD Datasheet

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DSP56303VF100: Description24-BIT, 100MHz, OTHER DSP, PBGA196, MOLDED ARRAY PROCESS, BGA-196; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，112 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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24-BIT, 100MHz, OTHER DSP, PBGA196, MOLDED ARRAY PROCESS, BGA-196

DSP56303VF100 Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
Parts packaging code	BGA
package instruction	LBGA, BGA196,14X14,40
Contacts	196
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	18
barrel shifter	YES
bit size	24
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	24
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PBGA-B196
length	15 mm
low power mode	YES
Number of terminals	196
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA196,14X14,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
RAM (number of words)	4096
Maximum seat height	1.6 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER

DSP56303VF100 Preview

Technical Data

DSP56303/D

Rev. 8, 4/2003

24-Bit Digital Signal

Processor

Memory Expansion Area

Triple

Timer

HI08

ESSI

SCI

PrograM

RAM

4096

bits

(default)

PM_EB

X Data

RAM

2048

bits

(default)

XM_EB

Y Data

RAM

2048

bits

(default)

YM_EB

PIO_EB

The

DSP56303

intended for use in

telecommunication

applications, such as

multi-line voice/data/

fax processing, video

conferencing, audio

applications, control,

and general digital

signal processing.

EXTAL

XTAL

Peripheral

Expansion Area

Address

Generation

Unit

Six-Channel

DMA Unit

Bootstrap

ROM

YAB

XAB

PAB

DAB

24-Bit

External

Address

Bus

Address

Switch

External

Bus

Interface

and Inst.

Cache Control

Control

External

Data Bus

Switch

Data

DSP56300

Core

DDB

YDB

XDB

PDB

GDB

Internal

Data

Bus

Switch

Clock

Generator

PLL

RESET

PINIT/NMI

Program

Interrupt

Controller

Program

Decode

Controller

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

Program

Address

Generator

24 + 56

→

56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Data ALU

Power

Management

JTAG

OnCE™

Figure 1.

DSP56303 Block Diagram

The

DSP56303

is a member of the DSP56300

core family of programmable CMOS Digital

Signal Processors (DSPs). This family uses a

high-performance, single clock cycle per

instruction engine providing a twofold

performance increase over Motorola’s popular

DSP56000 core family while retaining code

compatibility.

Significant architectural features of the

DSP56300 core family include a barrel shifter,

24-bit addressing, instruction cache, and

DMA. The

DSP56303

offers 100 MIPS using

an internal 100 MHz clock at 3.0–3.6 volts.

The DSP56300 core family offers a rich

instruction set and low power dissipation, as

well as increasing levels of speed and power

to enable wireless, telecommunications, and

multimedia products.

Table of Contents

DSP56303 Features............................................................................................................................................ iii

Target Applications ............................................................................................................................................ iv

Product Documentation...................................................................................................................................... iv

Chapter 1

Signal/ Connection Descriptions

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

1.10

1.11

1.12

1.13

Signal Groupings.............................................................................................................................................. 1-1

Power................................................................................................................................................................ 1-3

Ground.............................................................................................................................................................. 1-3

Clock ................................................................................................................................................................ 1-4

PLL................................................................................................................................................................... 1-4

External Memory Expansion Port (Port A)...................................................................................................... 1-5

Interrupt and Mode Control ............................................................................................................................. 1-8

Host Interface (HI08) ....................................................................................................................................... 1-9

Enhanced Synchronous Serial Interface 0 (ESSI0)........................................................................................ 1-13

Enhanced Synchronous Serial Interface 1 (ESSI1)........................................................................................ 1-14

Serial Communication Interface (SCI)........................................................................................................... 1-16

Timers............................................................................................................................................................. 1-17

JTAG and OnCE Interface ............................................................................................................................. 1-18

Introduction ...................................................................................................................................................... 2-1

Maximum Ratings............................................................................................................................................ 2-1

Thermal Characteristics ................................................................................................................................... 2-2

DC Electrical Characteristics ........................................................................................................................... 2-3

AC Electrical Characteristics ........................................................................................................................... 2-4

Pin-Out and Package Information .................................................................................................................... 3-1

TQFP Package Description .............................................................................................................................. 3-2

TQFP Package Mechanical Drawing ............................................................................................................... 3-9

MAP-BGA Package Description ................................................................................................................... 3-10

MAP-BGA Package Mechanical Drawing .................................................................................................... 3-19

Thermal Design Considerations....................................................................................................................... 4-1

Electrical Design Considerations ..................................................................................................................... 4-2

Power Consumption Considerations ................................................................................................................ 4-4

PLL Performance Issues .................................................................................................................................. 4-5

Input (EXTAL) Jitter Requirements................................................................................................................. 4-5

Chapter 2

Specifications

2.1

2.2

2.4

2.5

2.6

Chapter 3

Packaging

3.1

3.2

3.3

3.4

3.5

Chapter 4

Design Considerations

4.1

4.2

4.3

4.4

4.5

Appendix A

Index

Power Consumption Benchmark

Data Sheet Conventions

OVERBAR

“asserted”

“deasserted”

Examples:

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.)

Means that a high true (active high) signal is high or that a low true (active low) signal is low

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Signal/Symbol

Logic State

True

False

True

False

Signal State

Asserted

Deasserted

Asserted

Deasserted

Voltage

Note:

Values for V

, V

, and V

are defined by individual product specifications.

DSP56303 Features

High-Performance DSP56300 Core

• 100 million instructions per second (MIPS) with a 100 MHz clock at 3.3 V nominal

• Object code compatible with the DSP56000 core with highly parallel instruction set

• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24

24-bit parallel

Multiplier-Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream

generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under

software control

• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes

optimized for DSP applications (including immediate offsets), on-chip instruction cache controller,

on-chip memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts

• Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses;

one-, two-, and three-dimensional transfers (including circular buffering); end-of-block-transfer

interrupts; and triggering from interrupt lines and all peripherals

• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and

output clock with skew elimination

• Hardware debugging support including On-Chip Emulation (OnCE) module, Joint Test Action

Group (JTAG) Test Access Port (TAP)

On-Chip Peripherals

• Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of buses (for example,

ISA) and provides glueless connection to a number of industry-standard microcomputers,

microprocessors, and DSPs

• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters

(allows six-channel home theater)

• Serial communications interface (SCI) with baud rate generator

• Triple timer module

• Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which

peripherals are enabled

On-Chip Memories

• 192

24-bit bootstrap ROM

• 128 K RAM total

• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:

Program RAM

Size

4096

24-bit

3072

24-bit

2048

24-bit

1024

24-bit

Instruction

Cache Size

1024

24-bit

1024

24-bit

X Data RAM

Size

2048

24-bit

2048

24-bit

3072

24-bit

3072

24-bit

Y Data RAM

Size

2048

24-bit

2048

24-bit

3072

24-bit

3072

24-bit

Instruction

Cache

disabled

enabled

disabled

enabled

Switch Mode

disabled

enabled

iii

Off-Chip Memory Expansion

• Data memory expansion to two 256 K

24-bit word memory spaces using the standard external

address lines

• Program memory expansion to one 256 K

24-bit words memory space using the standard external

address lines

• External memory expansion port

• Chip Select Logic for glueless interface to static random access memory (SRAMs)

• On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs)

Reduced Power Dissipation

•

Very low-power CMOS design

Wait and Stop low-power standby modes

Fully static design specified to operate down to 0 Hz (dc)

Optimized power management circuitry (instruction-dependent, peripheral-dependent, and

mode-dependent)

Packaging

The DSP56303 is available in a 144-pin TQFP package or a 196-pin MAP-BGA package.

Target Applications

•

Multi-line voice/data/fax processing

Video conferencing

Audio applications

Control

Product Documentation

The three documents listed in the following table are required for a complete description of the

DSP56303 and are necessary to design properly with the part. Documentation is available from the

following sources. (See the back cover for details.)

•

A local Motorola distributor

A Motorola semiconductor sales office

A Motorola Literature Distribution Center

The World Wide Web (WWW)

Table 1.

DSP56303

Name

DSP56300 Family

Manual

DSP56303 User’s

Manual

DSP56303

Technical Data

Documentation

Order Number

DSP56300FM/AD

DSP56303UM/D

DSP56303/D

Description

Detailed description of the DSP56300 family processor core and

instruction set

Detailed functional description of the DSP56303 memory

configuration, operation, and register programming

DSP56303 features list and physical, electrical, timing, and

package specifications

Chapter 1

Signal/

Connection

Descriptions

1.1 Signal Groupings

The DSP56303 input and output signals are organized into functional groups as shown in

Table 1-1.

Figure 1-1

diagrams the DSP56303 signals by functional group. The remainder of this chapter describes

the signal pins in each functional group.

Table 1-1.

DSP56303 Functional Signal Groupings

Number of Signals

Functional Group

TQFP

Power (V

)

Ground (GND)

Clock

PLL

Address bus

Data bus

Bus control

Interrupt and mode control

Host interface (HI08)

Enhanced synchronous serial interface (ESSI)

Serial communication interface (SCI)

Timer

OnCE/JTAG Port

Notes:

Port B

Ports C and D

Port E

Port A

MAP-

BGA

Port A signals define the external memory interface port, including the external address bus, data

bus, and control signals.

Port B signals are the HI08 port signals multiplexed with the GPIO signals.

Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

Port E signals are the SCI port signals multiplexed with the GPIO signals.

There are 2 signal connections in the TQFP package and 7 signal connections in the MAP-BGA

package that are not used. These are designated as no connect (NC) in the package description

(see

Chapter 3).

Note:

This chapter refers to a number of configuration registers used to select individual multiplexed

signal functionality. Refer to the

DSP56303 User’s Manual

for details on these configuration

registers.

1-1

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DSP56303VF100 Related Products

	DSP56303VF100	DSP56303PV100	DSP56303VF100R2
Description	24-BIT, 100MHz, OTHER DSP, PBGA196, MOLDED ARRAY PROCESS, BGA-196	24-BIT, 100MHz, OTHER DSP, PQFP144, TQFP-144	24-BIT, 100MHz, OTHER DSP, PBGA196, MOLDED ARRAY PROCESS, BGA-196
Maker	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )
package instruction	LBGA, BGA196,14X14,40	LFQFP, QFP144,.87SQ,20	LBGA,
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	18	18	18
barrel shifter	YES	YES	YES
boundary scan	YES	YES	YES
maximum clock frequency	100 MHz	100 MHz	100 MHz
External data bus width	24	24	24
Format	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PBGA-B196	S-PQFP-G144	S-PBGA-B196
length	15 mm	20 mm	15 mm
low power mode	YES	YES	YES
Number of terminals	196	144	196
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LFQFP	LBGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage	3.6 V	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal form	BALL	GULL WING	BALL
Terminal pitch	1 mm	0.5 mm	1 mm
Terminal location	BOTTOM	QUAD	BOTTOM
width	15 mm	20 mm	15 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
Parts packaging code	BGA	-	BGA
Contacts	196	-	196
bit size	24	24	-
Encapsulate equivalent code	BGA196,14X14,40	QFP144,.87SQ,20	-
power supply	3.3 V	3.3 V	-
RAM (number of words)	4096	4096	-

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