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Openbus™ Interface Components - Universe User Manual
Copyright 196, Tundra Semiconductor Corporation
All rights reserved.
Document: 891042.MD300.05
Printed in Canada
® BI-mode is a registered trademark of DY-4 Systems Inc., denoting the Bus Isolation mode
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Table of Contents
1
General Information ............................................................................................ 1-1
1.1
1.2
1.3
1.4
Introduction............................................................................................. 1-1
Product Overview ................................................................................... 1-1
Using This Document ............................................................................. 1-3
Conventions ............................................................................................ 1-4
1.4.1
1.4.2
1.4.3
2
Signals .................................................................................... 1-4
Symbols.................................................................................. 1-4
Terminology ........................................................................... 1-4
Functional Description......................................................................................... 2-1
2.1
Architectural Overview........................................................................... 2-1
2.1.1
2.1.1.1
2.1.1.2
2.1.2
2.1.2.1
2.1.2.2
2.1.3
2.1.3.1
2.1.3.2
2.1.4
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
2.2.2.1
2.2.2.2
VMEbus Interface ................................................................. 2-3
Universe as VMEbus Slave ............................................ 2-3
Universe as VMEbus Master .......................................... 2-3
PCI Bus Interface ................................................................... 2-4
Universe as PCI Slave..................................................... 2-4
Universe as PCI Master .................................................. 2-4
Interrupter and Interrupt Handler ........................................... 2-4
Interrupter ....................................................................... 2-4
VMEbus Interrupt Handling ........................................... 2-5
DMA Controller ..................................................................... 2-5
VMEbus Requester ................................................................ 2-6
Internal Arbitration for VMEbus Requests..................... 2-6
Request Modes................................................................ 2-7
VMEbus Release............................................................. 2-8
Universe as VME Master ....................................................... 2-9
Addressing Capabilities .................................................. 2-9
Data Transfer Capabilities ............................................ 2-10
VMEbus Interface ................................................................................... 2-6
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This document was created with FrameMaker 4.0.4
2.2.2.3
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
2.2.3.6
2.2.3.7
2.2.4
2.2.4.1
2.2.4.2
2.2.5
2.2.5.1
2.2.5.2
2.2.6
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.4
2.2.7
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.1.5
2.3.1.6
2.3.2
2.3.2.1
Cycle Terminations ....................................................... 2-12
Universe as VME Slave ....................................................... 2-12
Coupled Transfers ......................................................... 2-13
Posted Writes ................................................................ 2-14
Prefetched Block Reads ................................................ 2-16
VMEbus Lock Commands............................................ 2-18
VMEbus Read Modify Writes ...................................... 2-18
Register Accesses.......................................................... 2-18
DTACK* Rescinding.................................................... 2-19
VMEbus Configuration ........................................................ 2-19
First Slot Detector ......................................................... 2-19
VMEbus Register Access at Power-up ......................... 2-19
Automatic Slot Identification ............................................... 2-20
Auto Slot ID: VME64 Specified................................... 2-20
Auto-ID: A Proprietary Tundra Method ....................... 2-21
System Controller Functions................................................ 2-22
System Clock Driver..................................................... 2-22
VMEbus Arbiter............................................................ 2-23
IACK Daisy-Chain Driver Module............................... 2-23
VMEbus Time-out ........................................................ 2-24
BI-Mode
®..................................................................................................
2-24
PCI Cycles - Overview......................................................... 2-25
32-Bit Versus 64-Bit PCI.............................................. 2-25
PCI Bus Request ........................................................... 2-26
Address Phase ............................................................... 2-26
Data Transfer ................................................................ 2-28
Termination Phase ........................................................ 2-28
Parity Checking............................................................. 2-29
Universe as PCI Master........................................................ 2-30
PCI Burst Transfers....................................................... 2-31
PCI Bus Interface .................................................................................. 2-25
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2.3.2.2
2.3.2.3
2.3.3
2.3.3.1
2.3.3.2
2.3.3.3
2.3.3.4
2.3.3.5
2.3.3.6
2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.1.3
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.3
2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.2.3
2.5.2.4
2.6
2.6.1
2.6.2
2.6.3
Termination................................................................... 2-32
Parity ............................................................................. 2-33
Universe as PCI Slave .......................................................... 2-33
Data Transfer ................................................................ 2-34
Coupled Transfers......................................................... 2-37
Posted Writes ................................................................ 2-38
RMW and ADOH Cycles ............................................. 2-40
Exclusive Accesses ....................................................... 2-41
Terminations ................................................................. 2-43
VME Slave Images .............................................................. 2-44
VMEbus Fields ............................................................. 2-45
PCI Bus Fields .............................................................. 2-45
Control Fields................................................................ 2-46
PCI Bus Slave Images .......................................................... 2-47
PCI Bus Fields .............................................................. 2-48
VMEbus Fields ............................................................. 2-48
Control Fields................................................................ 2-49
Special PCI Slave Image ...................................................... 2-49
Coupled Cycles .................................................................... 2-52
Decoupled Transactions ....................................................... 2-52
Posted Writes ................................................................ 2-52
Prefetched Reads........................................................... 2-54
DMA Errors .................................................................. 2-54
Parity Errors .................................................................. 2-55
The Interrupt Channel .......................................................... 2-56
PCI Interrupt Generation...................................................... 2-57
VMEbus Interrupt Generation.............................................. 2-59
Slave Image Programming.................................................................... 2-44
Bus Error Handling ............................................................................... 2-52
Interrupter.............................................................................................. 2-56
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