Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Programmable Timing Control Hub for P4 processor
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
•
2 - Pairs of differential CPUCLKs (differential current mode)
•
1 - SDRAM @ 3.3V
•
8 - PCI @3.3V
•
2 - AGP @ 3.3V
•
2 - ZCLKs @ 3.3V
•
1- 48MHz, @3.3V fixed.
•
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
•
3- REF @3.3V, 14.318MHz.
Features/Benefits:
•
Programmable output frequency, divider ratios, output
rise/falltime, output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I
2
C Index read/write and block read/write
operations.
•
For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
•
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
PCI - PCI output skew: < 500ps
•
CPU - SDRAM output skew: < 1ns
•
AGP - AGP output skew: <150ps
Pin Configuration
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDSD
SDRAM
GNDSD
CPU_STOP#*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL*
GND48
48-Pin 300-mil SSOP and TSSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
ICS952001
2
REF (1:0)
Functionality
B it 2 B it 7 B it 6 B it 5 B it 4
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(M H z )
6 6 .6 7
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
8 0 .0 0
8 0 .0 0
9 5 .0 0
9 5 .0 0
6 6 .6 7
SDRA M
(M H z )
6 6 .6 7
100.00
200.00
133.33
150.00
125.00
160.00
133.33
200.00
166.67
166.67
133.33
133.33
9 5 .0 0
126.67
6 6 .6 7
Z CLK
(M H z )
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 0 .0 0
6 2 .5 0
6 6 .6 7
8 0 .0 0
6 6 .6 7
6 2 .5 0
7 1 .4 3
6 6 .6 7
6 6 .6 7
6 3 .3 3
6 3 .3 3
5 0 .0 0
AGP
(M H z )
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
CPU
DIVDER
Stop
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
Control
Logic
ZCLK
DIVDER
ZCLK (1:0)
2
PCI
DIVDER
Stop
6
PCICLK (9:0)
PCICLK_F (1:0)
Config.
Reg.
2
AGP
DIVDER
2
AGP (1:0)
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
Note: For additional margin testing frequencies, refer to Byte 4
952001 Rev A 01/24/02
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General Description
The
ICS952001
is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero
delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks
signals for such a system.
The
ICS952001
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 11, 13, 19, 29,
42, 48
2
3
4
5, 8, 18, 24, 25,
32, 37, 41, 46
6
7
10, 9
12
14
15
23, 22, 21, 20, 17,
16
26
27
28, 36
30, 31
PIN NAME
VDD
FS0
TYPE
PWR
IN
Power supply for 3.3V
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Hyperzip clock outputs.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
MODE pin is in Mobile mode
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
PCI clock outputs.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Clock output for super I/O/USB default is 24MHz
48MHz output clock
Analog power supply 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.
When Vtt_PWRGD goes high the frequency select will be latched at
power on thereafter the pin is an asynchronous active low power down
pin.
2
Data pin for I C circuitry 5V tolerant
2
Clock pin of I C circuitry 5V tolerant
DESCRIPTION
REF0
FS1
OUT
IN
REF1
FS2
OUT
IN
REF2
GND
X1
X2
ZCLK(1:0)
PCI_STOP#
FS3
PCICLK_F0
FS4
PCICLK_F1
PCICLK (5:0)
MULTISEL
24_48MHz
48MHz
AVDD
AGPCLK (1:0)
PD#
OUT
PWR
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
OUT
IN
33
Vtt_PWRGD
34
35
38
SDATA
SCLK
IN
I/O
IN
I REF
OUT
This pin establishes the reference current for the CPUCLK
pairs. This pin requires a fixed precision resistor tied to ground
in order to establish the appropriate current.
"Complementary" clocks of differential pair CPU outputs. These clocks
are 180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase
with SDRAM clocks. These open drain outputs need an external 1.5V pull-
up.
Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile
mode
SDRAM clock output.
43, 39
CPUCLKC (1:0)
OUT
44, 40
45
47
CPUCLKT (1:0)
CPU_STOP#
SDRAM
OUT
IN
OUT
Third party brands and names are the property of their respective owners.
2
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
CPUCLK Swing Select Functions
MULTSEL0
0
0
0
0
1
1
1
1
Byte 23
Bit 7
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Reference R,
Iref=
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Output
Current
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 7*Iref
Ioh = 7*Iref
Voh @ Z,
Iref=2.32mA
0.71V @ 60
0.59V @ 50
0.56V @ 60
0.47V @ 50
0.85V /2 60
0.71V @ 50
0.99V @ 60
0.82V @ 50
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.60 @ 20
0.5V @ 20
0.90V @ 30
0.75V @ 20
1.05V @ 30
0.84V @ 20
Third party brands and names are the property of their respective owners.
3
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General I
2
C serial interface information for the ICS952001
How to Write:
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page
.
Third party brands and names are the property of their respective owners.
4
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer.
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4
FS4 FS3 FS2
FS1
FS0
CPU
SDRAM
ZCLK
0
0
0
0
0
66.67
66.67
66.67
0
0
0
0
1
100.00
100.00
66.67
0
0
0
1
0
100.00
200.00
66.67
0
0
0
1
1
100.00
133.33
66.67
0
0
1
0
0
100.00
150.00
60.00
0
0
1
0
1
100.00
125.00
62.50
0
0
1
1
0
100.00
160.00
66.67
0
0
1
1
1
100.00
133.33
80.00
0
1
0
0
0
100.00
200.00
66.67
0
1
0
0
1
100.00
166.67
62.50
0
1
0
1
0
100.00
166.67
71.43
0
1
0
1
1
80.00
133.33
66.67
0
1
1
0
0
80.00
133.33
66.67
95.00
95.00
63.33
0
1
1
0
1
95.00
126.67
63.33
0
1
1
1
0
66.67
66.67
50.00
0
1
1
1
1
1
0
0
0
0
105.00
140.00
70.00
1
0
0
0
1
100.90
100.90
67.27
1
0
0
1
0
108.00
144.00
72.00
1
0
0
1
1
100.90
134.53
67.27
1
0
1
0
0
112.00
149.33
74.67
1
0
1
0
1
133.33
100.00
66.67
1
0
1
1
0
133.33
133.33
66.67
1
0
1
1
1
133.33
166.67
66.67
1
1
0
0
0
100.00
133.00
80.00
1
1
0
0
1
100.00
100.00
80.00
1
1
0
1
0
100.00
166.67
83.33
1
1
0
1
1
133.33
160.00
80.00
1
1
1
0
0
100.00
133.00
100.00
100.00
100.00
100.00
1
1
1
0
1
1
1
1
1
0
100.00
166.67
100.00
1
1
1
1
1
133.33
160.00
100.00
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
AGP
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
70.00
67.27
72.00
67.27
74.67
66.67
66.67
66.67
66.67
66.67
62.50
66.67
66.67
66.67
62.50
66.67
PCI
33.33
33.33
33.33
33.33
30.00
31.25
33.33
33.33
33.33
31.25
41.67
33.33
33.33
31.67
31.67
25.00
35.00
33.63
36.00
33.63
37.33
33.33
33.33
33.33
33.33
33.33
31.25
33.33
33.33
33.33
31.25
33.33
Spread Precentage
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
PWD
Bit 2
Bit 7:4
00000
Note1
Bit 3
Bit 1
Bit 0
0
0
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note:
PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
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