White Electronic Designs
W78M64VP-XSBX
8Mx64 Flash 3.3V Page Mode Multi-Chip Package
FEATURES
Access Times of 110, 120ns
Packaging
• 159 PBGA, 13x22mm – 1.27mm pitch
Page Mode
• Page size is 8 words: Fast page read access from
random locations within the page.
Uniform Sector Architecture
• One hundred twenty-eight 64 kword
Single power supply operation
• 3 volt read, erase, and program operations
I/O Control
• All input levels (address, control, and DQ input
levels) and outputs are determined by voltage on
V
IO
input.
Write operation status bits indicate program and
erase operation completion
Suspend and Resume commands for program and
erase operations
Hardware Reset# input resets device
WP#/ACC Input
• Accelerates programming time for greater
throughput.
• Protects
fi
rst and last sector regardless of sector
protection settings
* This product is subject to change without notice.
Secured Silicon Sector region
• 128-word sector for permanent, secure
identification through an 8-word random Electronic
Serial Number, accessible through a command
sequence
• May be programmed and locked at the factory or
by the customer
100,000 erase cycles per sector typical
20-year data retention typical
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2009
Rev. 10
© 2010 White Electronic Designs Corp. All rights reserved
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FIG 1: PIN CONFIGURATION
FOR W78M64VP-XSBX (TOP VIEW)
W78M64VP-XSBX
FIG 2: PIN DESCRIPTION
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
IO
2
GND
3
GND
4
GND
5
V
CC
6
V
IO
7
GND
8
GND
9 10
GND
V
CC
GND
DQ41
WE
3
#
V
IO
DQ57
DNU
WE
4
#
V
CC
V
IO
V
CC
DQ33
DQ43
DQ45
DQ47
DQ49
DQ59
DQ61
DQ63
V
CC
DQ
0-63
A
0-22
WE#
1-4
CS#
1-4
OE#
RESET#
WP#/ACC
RY/BY#
V
CC
V
IO
GND
DNU
V
IO
DQ40
DQ35
DQ37
DQ39
DQ56
DQ51
DQ53
DQ55
V
IO
V
CC
DQ32
DQ42
DQ44
DQ46
DQ48
DQ58
DQ60
DQ62
V
CC
GND
CS
3
#
DQ34
DQ36
DQ38
CS
4
#
DQ50
DQ52
DQ54
GND
GND
OE#
A0
A22
V
CC
A12
A16
A21
A20
GND
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Hardware Reset
Hardware Write
Protection/Acceleration
Ready/Busy Output
Power Supply
Versatile I/O Input
Ground
Do Not Use
GND
A2
WP#/A
CC
A11
GND
V
IO
A7
A10
A15
GND
GND
A3
A6
A9
V
CC
GND
A1
RESET#
A13
GND
GND
A4
A17
RY/BY#
GND
A14
A5
A18
A8
GND
GND
DQ
17
WE
2
#
DQ29
DNU*
DQ9
DQ4
WE
1
#
A19
GND
FIG 3: BLOCK DIAGRAM
WE1#
WE2#
CS2#
WE3#
CS3#
WE4#
CS4#
CS1#
V
IO
DQ24
DQ19
DQ21
DQ31
DQ1
DQ11
DQ6
DQ15
V
IO
RY/BY#
RESET#
OE#
A
0-22
V
CC
DQ16
DQ26
DQ28
DQ23
DQ8
DQ3
DQ13
DQ7
V
CC
V
IO
CS2#
DQ18
DQ20
DQ30
DQ0
DQ10
DQ5
DQ14
V
IO
8M X 16
8M X 16
8M X 16
8M X 16
V
CC
V
CC
DQ25
DQ27
DQ22
CS
1
#
DQ2
DQ12
GND
V
CC
WP#/ACC
V
IO
GND
GND
GND
V
IO
V
CC
GND
GND
GND
V
IO
DQ
0-15
DQ
16-31
DQ
32-47
DQ
48-63
* Ball L5 is reserved for A23 for future upgrades.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2009
Rev. 10
© 2010 White Electronic Designs Corp. All rights reserved
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
GENERAL DESCRIPTION
The W78M64VP-XSBX is a 512Mb, 3.3 volt-only Page
Mode memory device.
The device offers fast page access times allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip
enable (CS#), write enable (WE#) and output enable (OE#)
controls.
The device offers uniform 64 Kword (128Kb) Sectors:
W78M64VP-XSBX
DEVICE OPERATION TABLE
The device must be setup appropriately for each operation.
Table 2 describes the required state of each control pin for
any particular operation.
READ
All memories require access time to output array data. In a
read operation, data is read from one memory location at
a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes
the data on its outputs to arrive with the address on its inputs.
The device defaults to reading array data after device power-
up or hardware reset. To read data from the memory array,
the system must
fi
rst assert a valid address on A22-A0,
while driving OE# and CE# to V
IL
. WE# must remain at
V
IH
. All addresses are latched on the falling edge of CE#.
Data will appear on DQ15-DQ0 after address access time
(t
ACC
), which is equal to the delay from stable addresses
to valid output data.
The OE# signal must be driven to V
IL
. Data is output on
DQ15-DQ0 pins after the access time (t
OE
) has
elapsed from the falling edge of OE#, assuming the t
ACC
access time has been meet.
PAGE MODE FEATURES
The page size is 8 words. After initial page access is
accomplished, the page mode operation provides fast read
access speed of random locations within that page.
STANDARD FLASH MEMORY
FEATURES
The device requires a 3.3 volt power supply for both read
and write functions. Internally generated and regulated
voltages are provided for the program and erase operations
Page Mode Features
DEVICE OPERATIONS
This section describes the read, program, erase,
handshaking, and reset features of the Flash devices.
Operations are initiated by writing specific commands or
a sequence with specific address and data patterns into
the command registers ( see Table 38 and Table 39). The
command register itself does not occupy andy addressable
memory location; rather, it is composed of latches that store
the commands, along with the address and data information
needed to execute the command. The contents of the
register serves as input to the internal state machine and
the state machine outputs dictate the function of the device.
Writing incorrect address and data values or writing them in
an improper sequence may place the device in an unknown
state, in which case the system must pull the RESET# pin
low or power cycle the device to return the device to the
reading array data mode.
PAGE READ MODE
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random
locations within a page. The page size of the device is
8 words. The appropriate page is selected by the higher
address bits A(22)-A3.
Address bits A2-A0 in word mode determine the specific
word within a page. The microprocessor supplies the
specific word location. The random or initial page access
is equal to t
ACC
or t
CE
and subsequent page read accesses
(as long as the locations specified by the microprocessor
falls within that page) is equivalent to t
ACC
. When CE# is
deasserted and reasserted for a subsequent access, the
access time is t
ACC
or t
CE
. Fast page mode accesses are
obtained by keeping the “read-page addresses” constant
and changing the “intra-read page” addresses.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2009
Rev. 10
© 2010 White Electronic Designs Corp. All rights reserved
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
AUTOSELECT
The Autoselect mode provides manufacturer ID, Device
identification, and sector protection information, through
identifier codes output from the internal register (separate
from the memory array) on DQ7-DQ0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm (see Table 4). The Autoselect codes
can also be accessed in-system.
There are two methods to access autoselect codes. One
uses the autoselect command, the other applies V
ID
on
address pin A9.
When using programming equipment, the autoselect mode
requires V
ID
(11.5 V to 12.5 V) on address pin A9. Address
pins must be as shown in Table 3.
To access Autoselect mode without using high
voltage on A9, the host system must issue the
Autoselect command.
The Autoselect command sequence may be written
to an address within a sector that is either in the read
or erase-suspend-read mode.
The Autoselect command may not be written while
the device is actively programming or erasing.
The system must write the reset command to return
to the read mode (or erase-suspend-read mode if the
sector was previously in Erase Suspend).
It is recommended that A9 apply V
ID
after power-
up sequence is completed. In addition, it is
recommended that A9 apply from V
ID
to V
IH
/V
IL
before power-down the V
CC
/V
IO
.
See Table 39 for command sequence details.
When verifying sector protection, the sector address
must appear on the appropriate highest order
address bits (see Table 5 to Table 6). The remaining
address bits are don't care. When all necessary
bits have been set as required, the programming
equipment may then read the corresponding
identifier code on DQ15-DQ0. The Autoselect
codes can also be accessed in-system through the
command register.
W78M64VP-XSBX
PROGRAM/ERASE OPERATIONS
These devices are capable of several modes of programming
and or erase operations which are described in detail in the
following sections.
During a write operation, the system must drive CE#
and WE# to V
IL
and OE# to V
IH
when providing address,
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the
1st rising edge of WE# or CE#.
The Unlock Bypass feature allows the host system to send
program commands to the Flash device without
fi
rst writing
unlock cycles within the command sequence. See Unlock
Bypass section for details on the Unlock Bypass function.
Note the following:
When the Embedded Program algorithm is complete,
the device returns to the read mode.
The system can determine the status of the program
operation by reading the DQ status bits. Refer to
the Write Operation Status for information on these
status bits.
An “0” cannot be programmed back to a “1.” A
succeeding read shows that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the
Embedded Program/Erase are ignored except the
Suspend commands.
Secured Silicon Sector, Autoselect, and CFI
functions are unavailable when a program operation
is in progress.
A hardware reset and/or power removal immediately
terminates the Program/Erase operation and the
Program/Erase command sequence should be
reinitiated once the device has returned to the read
mode to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries for single word programming
operation. See Write Buffer Programming when
using the write buffer.
Programming to the same word address multiple
times without intervening erases is permitted.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2009
Rev. 10
© 2010 White Electronic Designs Corp. All rights reserved
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
SINGLE WORD PROGRAMMING
Single word programming mode is one method of
programming the Flash. In this mode, four Flash command
write cycles are used to program an individual Flash
address. The data for this programming operation could
be 8 or 16-bits wide.
While the single word programming method is supported
by most Spansion devices, in general Single Word
Programming is not recommended for devices that support
Write Buffer Programming. See Table 38 for the required bus
cycles and FIG: 4 for the
fl
owchart. When the Embedded
Program algorithm is complete, the device then returns to
the read mode and addresses are no longer latched. The
system can determine the status of the program operation
by reading the DQ status bits. Refer to Write Operation
Status for information on these status bits.
During programming, any command (except the
Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI
functions are unavailable when a program operation
is inprogress.
A hardware reset immediately terminates the
program operation. The program command
sequence should
be reinitiated once the device has returned to the
read mode, to ensure data integrity.
Programming to the same address multiple times
continuously (for example, “walking” a bit within a
word) is permitted.
W78M64VP-XSBX
the operation aborts. (Number loaded = the number of
locations to program minus 1. For example, if the system
programs 6 address locations, then 05h should be written
to the device.)
The system then writes the starting address/data
combination. This starting address is the
fi
rst address/data
pair to be programmed, and selects the “write-buffer-page”
address. All subsequent address/data pairs must fall within
the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses
AMAX–A5.
The “write-buffer-page” addresses must be the same for all
address/data pairs loaded into the write buffer. (This means
Write Buffer Programming cannot be performed across
multiple “write-buffer-pages.” This also means that Write
Buffer Programming cannot be performed across multiple
sectors. If the system attempts to load programming data
outside of the selected “write-buffer-page”, the operation
ABORTs.)
After writing the Starting Address/Data pair, the system then
writes the remaining address/data pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple
times, the “address/data pair” counter is decremented for
every data load operation. Also, the last data loaded at
a location before the “Program Buffer to Flash” confirm
command is the data programmed into the device. It is
the software's responsibility to comprehend ramifications
of loading a write-buffer location more than once. The
counter decrements for each data load operation, NOT
for each unique write-buffer-address location. Once the
specified number of write buffer locations have been loaded,
the system must then write the “Program Buffer to Flash”
command at the Sector Address. Any other address/data
write combinations abort the Write Buffer Programming
operation. The Write Operation Status bits should be used
while monitoring the last address location loaded into the
write buffer. This eliminates the need to store an address
in memory because the system can load the last address
location, issue the program confirm command at the last
loaded address location, and then check the write operation
status at that same address. DQ7, DQ6, DQ5, DQ2, and
DQ1 should be monitored to determine the device status
during Write Buffer Programming.
The write-buffer “embedded” programming operation
can be suspended using the standard suspend/resume
commands. Upon successful completion of the Write Buffer
Programming operation, the device returns to READ mode.
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WRITE BUFFER PROGRAMMING
Write Buffer Programming allows the system to write a
maximum of 32 words in one programming operation. This
results in a faster effective word programming time than the
standard “word” programming algorithms.
The Write Buffer Programming command sequence is
initiated by
fi
rst writing two unlock cycles. This is followed by
a third write cycle containing the Write Buffer Load command
written at the Sector Address in which programming occurs.
At this point, the system writes the number of “word locations
minus 1” that are loaded into the page buffer at the Sector
Address in which programming occurs. This tells the
device how many write buffer addresses are loaded with
data and therefore when to expect the “Program Buffer
to Flash” confirm command. The number of locations
to program cannot exceed the size of the write buffer or
November 2009
Rev. 10
© 2010 White Electronic Designs Corp. All rights reserved
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
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