QL12X16B-0PF100C datasheet, PDF

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QL12X16B-0PF100C: DescriptionField Programmable Gate Array, 192 CLBs, 2000 Gates, 150MHz, 192-Cell, CMOS, PQFP100, TQFP-100; CategoryProgrammable logic devices Programmable logic; File Size651KB，11 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL12X16B-0PF100C Overview

Field Programmable Gate Array, 192 CLBs, 2000 Gates, 150MHz, 192-Cell, CMOS, PQFP100, TQFP-100

QL12X16B-0PF100C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	QFP
package instruction	LFQFP, QFP100,.63SQ,20
Contacts	100
Reach Compliance Code	unknown
Other features	MAX 80 I/OS
maximum clock frequency	150 MHz
Combined latency of CLB-Max	8.06 ns
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Configurable number of logic blocks	192
Equivalent number of gates	2000
Number of entries	88
Number of logical units	192
Output times	80
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
organize	192 CLBS, 2000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

QL12X16B-0PF100C Preview

QL12X16B

pASIC

1 Family

Very-High-Speed CMOS FPGA

Rev C

pASIC

HIGHLIGHTS

Very High Speed

– ViaLink

metal-to-metal programmable–via

antifuse technology, allows counter speeds over 150 MHz and logic

cell delays of under 2 ns.

High Usable Density

– A 12-by-16 array of 192 logic cells

provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and

84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages.

Low-Power, High-Output Drive

– Standby current typically 2

mA. A 16-bit counter operating at 100 MHz consumes less than 50

mA. Minimum IOL of 12 mA and IOH of 8 mA

Low-Cost, Easy-to-Use Design Tools

– Designs entered and

simulated using QuickLogic's new QuickWorks

development

environment, or with third-party CAE tools including Viewlogic,

Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place

and route on PC and workstation platforms using QuickLogic

software.

…2,000

usable ASIC gates,

88 I/O pins

pASIC 1

QL12x16B

Block Diagram

192 Logic Cells

= Up to 80 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells

4-13

QL12x16B

PRODUCT

SUMMARY

The QL12x16B is a member of the pASIC 1 Family of very-high-speed

CMOS user-programmable ASIC devices. The 192 logic cell field-

programmable gate array (FPGA) offers 2,000 usable ASIC gates (4,000

usable PLD gates) of high-performance general-purpose logic in a wide

variety of package configurations.

Low-impedance, metal-to-metal, ViaLink interconnect technology

provides nonvolatile custom logic capable of operating above 150 MHz.

Logic cell delays under 2 ns, combined with input delays of under 1.5 ns

and output delays under 3 ns, permit high-density programmable devices

to be used with today’s fastest microprocessors and DSPs.

Designs can be entered using QuickLogic’s QuickWorks Toolkit or most

populart third-party CAE tools. QuickWorks combines Verilog/VHDL

design entry and simulation tools with device-specific place & route and

programming software. Ample on-chip routing channels allow fast, fully

automatic place and route of designs using up to 100% of the logic and

I/O cells, while maintaining fixed pin-outs.

FEATURES

Total of 88 I/O pins

– 80 Bidirectional Input/Output pins

– 6 Dedicated Input/High-Drive pins

– 2 Clock/Dedicated input pins with fanout-independent, low-skew

clock networks

Input + logic cell + output delays under 6 ns

Chip-to-chip operating frequencies up to 110 MHz

Internal state machine frequencies up to 150 MHz

Clock skew < 0.5 ns

Input hysteresis provides high noise immunity

Built-in scan path permits 100% factory testing of logic and I/O cells

and functional testing with Automatic Test Vector Generation

(ATVG) software after programming

Available in 68-pin and 84-pin PLCC, 84-pin CPGA and 100-pin

TQFP packages

68-pin PLCC compatible with QL8x12B

84-pin PLCC compatible with QL16x24B

100-pin TQFP compatible with QL8x12B and QL16x24B

0.65µ CMOS process with ViaLink programming technology

4-14

QL12x16B

Pinout

Diagram

68-pin PLCC

pASIC 1

Pinout

Diagram

84-pin PLCC

Pins identified I/SCLK, SM, SO and SI are used during scan path testing operation.

4-15

QL12x16B

Pinout Diagram

84-pin CPGA

CPGA 84 Function/Connector Pin Table

B10

A10

FUNC

GND

I/(SCLK)

I/CLK/(SM)

I(P)

VCC

FUNC

GND

VCC

L10

L11

FUNC

GND

I/(SI)

I/CLK

I/(SO)

VCC

K10

J10

K11

J11

H10

H11

G11

G10

F11

F10

E11

E10

D11

D10

C11

B11

C10

A11

FUNC

GND

VCC

4-16

QL12x16B

Pinout Diagram

100-pin TQFP

pASIC 1

4-17

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