3-level inputs for feedback divide selection multiply /
divide ratios of (1-6, 8, 10, 12) / (2, 4)
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Power-down mode
Lock indicator
Available in TQFP package
Not Recommended for New Design
IDT5V995
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014
DESCRIPTION:
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The IDT5V995 is a high fanout 3.3V PLL based clock driver
intended for high performance computing and data-communica-
tions applications. A key feature of the programmable skew is the
ability of outputs to lead or lag the REF input signal. The
IDT5V995 has eight programmable skew outputs in four banks of
2. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from 1 to 12
through the use of the DS[1:0] inputs. This provides the user with
frequency multiplication from 1 to 12 without using divided
outputs for feedback.
When the sOE pin is held low, all the outputs are synchro-
nously enabled. However, if sOE is held high, all the outputs
except 2Q0 and 2Q1 are synchronously disabled. The LOCK
output asserts to indicate when Phase Lock has been achieved.
Furthermore, when PE is held high, all the outputs are synchro-
nized with the positive edge of the REF clock input. When PE is
held low, all the outputs are synchronized with the negative edge
of REF. The IDT5V995 has LVTTL outputs with 12mA balanced
drive outputs.
PE
TE ST
FS
LOC K
FUNCTIONAL BLOCK DIAGRAM
R EF
FB
3
DS 1:0
PD
sOE
3
/N
3
P LL
3
3
1F1:0
3
S kew
Select
1Q
0
1Q
1
3
2F1:0
3
S kew
Select
2Q
0
2Q
1
3
3F1:0
3
S kew
Select
3Q
0
3Q
1
3
4F1:0
3
S kew
Select
4Q
0
4Q
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT
™
/ ICS
™
PLL CLOCK DRIVER TURBOCLOCK™ II
1
IDT5V995 REV. B
DECEMBER 20, 2013
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II
PIN CONFIGURATION
TE ST
RE F
V
DD
G ND
4F
0
3F
1
3F
0
2F
1
2F
0
1F
1
FS
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, V
DD
V
I
Description
Supply Voltage to Ground
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
T
STG
T
A
= 85°C
T
A
= 55°C
Max
–0.5 to +4.6
–0.5 to V
DD
+0.5
–0.5 to +5.5
0.7
1.1
–65 to +150
°C
Unit
V
V
V
W
44
4F
1
sOE
PD
PE
V
D D Q
V
D D Q
4Q
1
4Q
0
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1F
0
DS
1
DS
0
LO CK
V
DD Q
V
DD Q
1Q
0
1Q
1
G ND
GND
GND
Storage Temperature Range
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-
manent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-
tions for extended periods may affect device reliability.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
Description
Typ.
5
Max.
7
Unit
pF
C
IN
Input Capacitance
13
14
15
16
17
18
19
20
21
22
V
D D Q
V
D D Q
G ND
V
D DQ
V
D DQ
G ND
3Q
1
3Q
0
FB
2Q
1
2Q
0
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF
[1:0]
, and DS
[1:0]
.
TQFP
TOP VIEW
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
sOE
(1)
Type
IN
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control
Summary Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q
0
and 2Q
1
) in a LOW state (for PE = H) - 2Q
0
and
2Q
1
may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
sOE
is HIGH, the nF[
1:0
]
pins act as output disable controls for individual banks when nF[
1:0
] = LL. Set
sOE
LOW for normal operation (has internal pull
down).
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of
reference clock (has internal pull-up).
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
Four banks of two outputs with programmable skew
3-level inputs for feedback divider selection
Power down control. Shuts off entire chip when LOW (has internal pull-up).
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized
PE
the
nF
[1:0]
FS
nQ
[1:0]
DS
[1:0]
PD
LOCK
to
IN
IN
IN
OUT
IN
IN
OUT
the inputs. (For more information on application specific use of the LOCK pin, please see AN237.)
PWR
Power supply for output buffers
V
DDQ
V
1.
PWR
Power supply for phase
active with nF[
1:0
] LL functioning as an output
circuitry
NOTE:
DD
When TEST = MID and
sOE
= HIGH, PLL remains
locked loop, lock
=
output, and other internal
disable control for individual output banks. Skew selections remain in
effect
GND
nF[
1:0
] = LL.
unless
PWR
Ground
IDT
™
/ ICS
™
PLL CLOCK DRIVER TURBOCLOCK™ II
2
IDT5V995 REV. B
DECEMBER 20, 2013
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to
compensate for PCB trace delays, backplane propagation de-
lays or to accommodate requirements for special timing rela-
tionships between clocked components. Skew is selectable as
a multiple of a time unit (tu) which ranges from 625ps to 1.3ns
(see Programmable Skew Range and Resolution Table). There
are nine skew configurations available for each output pair.
These configurations are chosen by the nF1:0 control pins. In
order to minimize the number of control pins, 3-level inputs
(HIGH-MID-LOW) are used, they are intended for but not re-
stricted to hard-wiring. Undriven 3-level inputs default to the
MID level. Where programmable skew is not a requirement,
the control pins can be left open for the zero skew default
setting. The Control Summary Table shows how to select spe-
cific skew taps by using the nF1:0 control pins.
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V995 gives users
flexibility with regard to skew adjustment. The FB signal is
compared with the input REF signal at the phase detector in
order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to
the phase detector. The loop filter transfer function has been
chosen to provide minimal jitter (or frequency variation) while
still providing accurate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±7.8125ns
±67.5°
±18.75%
Example 1, F
NOM
= 25MHz
Example 2, F
NOM
= 37.5MHz
Example 3, F
NOM
= 50MHz
Example 4, F
NOM
= 75MHz
Example 5, F
NOM
= 100MHz
Example 6, F
NOM
= 150MHz
Example 7, F
NOM
= 200MHz
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
—
—
±7.8125ns
±135°
±37.5%
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
±7.8125ns
±270°
±75%
—
—
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
ns
Phase Degrees
% of Cycle Time
1/(32 x F
NOM
)
24 to 50MHz
FS = MID
1/(16 x F
NOM
)
48 to 100MHz
FS = HIGH
1/(8 x F
NOM
)
96 to 200MHz
Comments
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q
1:0
, 2Q
1:0
, and the higher outputs
when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be F
NOM
when the output connected to FB is undivided and DS[
1:0
] = MM. The
frequency of the REF and FB inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for frequency multiplication by using a divided output as the FB input and setting DS[
1:0
] = MM.
Using the DS[
1:0
] inputs allows a different method for frequency multiplication (see Divide Selection Table).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to
output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
IDT
™
/ ICS
™
PLL CLOCK DRIVER TURBOCLOCK™ II
3
IDT5V995 REV. B
DECEMBER 20, 2013
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II
DIVIDE SELECTION TABLE
DS [
1:0
]
LL
LM
LH
ML
MM
MH
HL
HM
HH
FB Divide-by-n
2
3
4
5
1
6
8
10
12
Permitted Output Divide-by-n connected to FB
(1)
1 or 2
1
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
1
NOTE: 1.Permissible
output division ratios connected to FB. The frequency of the REF input will be F
NOM
/N when the part is configured for frequency multiplication by using an
undivided output for FB and setting DS[
1:0
] to N (N = 1-6, 8, 10, 12).
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
LL
(1)
LM
LH
ML
MM
MH
HL
HM
HH
Skew (Pair #1, #2)
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
1t
U
2t
U
3t
U
4t
U
Skew (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Divide by 4
Skew (Pair #4)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Inverted
(2)
NOTES: 1. LL DISABLES OUTPUTS IF TEST = MID AND
SOE
= HIGH.
2.
When pair #4 is set to HH (inverted),
sOE
disables pair #4 HIGH when PE = HIGH,
sOE
disables pair #4 LOW when PE = LOW.
RECOMMENDED OPERATING RANGE
Symbol
V
DD
/V
DDQ
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
3
-40
Typ.
3.3
+25
Max.
3.6
+85
Unit
V
°C
IDT
™
/ ICS
™
PLL CLOCK DRIVER TURBOCLOCK™ II
4
IDT5V995 REV. B
DECEMBER 20, 2013
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II
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