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FQB6N80TM

Description
5.8A, 800V, 1.95ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB, D2PAK-3
CategoryDiscrete semiconductor    The transistor   
File Size1MB,12 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Environmental Compliance
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FQB6N80TM Overview

5.8A, 800V, 1.95ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB, D2PAK-3

FQB6N80TM Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerRochester Electronics
Parts packaging codeD2PAK
package instructionD2PAK-3
Contacts3
Reach Compliance Codeunknown
Avalanche Energy Efficiency Rating (Eas)680 mJ
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage800 V
Maximum drain current (ID)5.8 A
Maximum drain-source on-resistance1.95 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JEDEC-95 codeTO-263AB
JESD-30 codeR-PSSO-G2
JESD-609 codee3
Humidity sensitivity level1
Number of components1
Number of terminals2
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)245
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)23.2 A
Certification statusCOMMERCIAL
surface mountYES
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal locationSINGLE
Maximum time at peak reflow temperature30
transistor applicationsSWITCHING
Transistor component materialsSILICON

FQB6N80TM Preview

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FQB6N80 / FQI6N80
September 2000
QFET
FQB6N80 / FQI6N80
800V N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.
TM
Features
5.8A, 800V, R
DS(on)
= 1.95Ω @V
GS
= 10 V
Low gate charge ( typical 31 nC)
Low Crss ( typical 14 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
D
D
!
"
G
S
G
!
3 5
"
"
D
2
-PAK
FQB Series
G D S
I
2
-PAK
FQI Series
!
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
C
= 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (T
C
= 25°C)
Drain Current
- Continuous (T
C
= 100°C)
Drain Current
- Pulsed
(Note 1)
FQB6N80 / FQI6N80
800
5.8
3.67
23.2
±
30
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
A
= 25°C) *
Power Dissipation (T
C
= 25°C)
680
5.8
15.8
4.0
3.13
158
1.27
-55 to +150
300
T
J
, T
STG
T
L
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
R
θJC
R
θJA
R
θJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
Typ
--
--
--
Max
0.79
40
62.5
Units
°C/W
°C/W
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A, September 2000
FQB6N80 / FQI6N80
Electrical Characteristics
Symbol
Parameter
T
C
= 25°C unless otherwise noted
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
∆BV
DSS
/
∆T
J
I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
V
GS
= 0 V, I
D
= 250
µA
I
D
= 250
µA,
Referenced to 25°C
V
DS
= 800 V, V
GS
= 0 V
V
DS
= 640 V, T
C
= 125°C
V
GS
= 30 V, V
DS
= 0 V
V
GS
= -30 V, V
DS
= 0 V
800
--
--
--
--
--
--
0.9
--
--
--
--
--
--
10
100
100
-100
V
V/°C
µA
µA
nA
nA
On Characteristics
V
GS(th)
R
DS(on)
g
FS
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Forward Transconductance
V
DS
= V
GS
, I
D
= 250
µA
V
GS
= 10 V, I
D
= 2.9 A
V
DS
= 50 V, I
D
= 2.9 A
(Note 4)
3.0
--
--
--
1.5
5.9
5.0
1.95
--
V
S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
--
--
--
1150
125
14
1500
160
18
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 640 V, I
D
= 5.8 A,
V
GS
= 10 V
(Note 4, 5)
V
DD
= 400 V, I
D
= 5.8 A,
R
G
= 25
(Note 4, 5)
--
--
--
--
--
--
--
30
70
65
45
31
7.1
15
70
150
140
100
--
--
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
V
GS
= 0 V, I
S
= 5.8 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS
= 0 V, I
S
= 5.8 A,
dI
F
/ dt = 100 A/µs
(Note 4)
--
--
--
--
--
--
--
--
650
5.7
5.8
23.2
1.4
--
--
A
A
V
ns
µC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 38mH, I
AS
= 5.8A, V
DD
= 50V, R
G
= 25
Ω,
Starting T
J
= 25°C
3. I
SD
5.8A, di/dt
200A/µs, V
DD
BV
DSS,
Starting T
J
= 25°C
4. Pulse Test : Pulse width
300µs, Duty cycle
2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A, September 2000
FQB6N80 / FQI6N80
Typical Characteristics
10
1
I
D
, Drain Current [A]
I
D
, Drain Current [A]
V
GS
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V
Top :
10
1
150 C
o
o
10
0
25 C
10
0
-55 C
o
10
-1
Notes :
1. 250μ Pulse Test
s
2. T
C
= 25℃
Notes :
1. V
DS
= 50V
2. 250μ Pulse Test
s
10
-1
10
0
10
1
10
-1
2
4
6
8
10
V
DS
, Drain-Source Voltage [V]
V
GS
, Gate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
4
V
GS
= 10V
10
1
R
DS(ON)
[Ω ],
Drain-Source On-Resistance
V
GS
= 20V
2
I
DR
, Reverse Drain Current [A]
3
10
0
1
150℃
25℃
Notes :
1. V
GS
= 0V
2. 250μ Pulse Test
s
Note : T
J
= 25℃
0
0
4
8
12
16
10
-1
0.2
0.4
0.6
0.8
1.0
1.2
I
D
, Drain Current [A]
V
SD
, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
2000
1800
1600
1400
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
12
10
V
DS
= 160V
V
DS
= 400V
V
GS
, Gate-Source Voltage [V]
C
iss
8
V
DS
= 640V
Capacitance [pF]
1200
1000
800
600
400
200
0
-1
10
C
oss
Notes :
1. V
GS
= 0 V
2. f = 1 MHz
6
4
C
rss
2
Note : I
D
= 5.8A
10
0
10
1
0
0
5
10
15
20
25
30
35
V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A, September 2000
FQB6N80 / FQI6N80
Typical Characteristics
(Continued)
1.2
3.0
2.5
BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
R
DS(ON)
, (Normalized)
Drain-Source On-Resistance
1.1
2.0
1.0
1.5
1.0
Notes :
1. V
GS
= 10 V
2. I
D
= 2.9 A
0.9
Notes :
1. V
GS
= 0 V
A
2. I
D
= 250
μ
0.5
0.8
-100
-50
0
50
100
o
150
200
0.0
-100
-50
0
50
100
o
150
200
T
J
, Junction Temperature [ C]
T
J
, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
6
10
2
Operation in This Area
is Limited by R
DS(on)
5
10
1
I
D
, Drain Current [A]
DC
10
0
I
D
, Drain Current [A]
3
10μ
s
100μ
s
1 ms
10 ms
4
3
2
10
-1
Notes :
1. T
C
= 25 C
2. T
J
= 150 C
3. Single Pulse
o
o
1
10
-2
10
0
10
1
10
2
10
0
25
50
75
100
125
150
V
DS
, Drain-Source Voltage [V]
T
C
, Case Temperature [
]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs Case Temperature
( t) , T h e r m a l R e s p o n s e
10
0
D = 0 .5
N o te s :
1 . Z
θ
J C
( t) = 0 .7 9
/ W M a x .
2 . D u ty F a c to r , D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
θ
J C
( t)
0 .2
10
-1
0 .1
0 .0 5
0 .0 2
0 .0 1
s i n g le p u ls e
P
DM
t
1
t
2
Z
θ
JC
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t
1
, S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, September 2000

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