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Datasheet> All Categories > Other integrated circuit (IC)> Consumption circuit> AD9801JCSTRL
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AD9801JCSTRL

Description
SPECIALTY CONSUMER CIRCUIT, PQFP48, 1.40 MM HEIGHT, PLASTIC, TQFP-48
CategoryOther integrated circuit (IC)    Consumption circuit   
File Size945KB，14 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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AD9801JCSTRL Overview

SPECIALTY CONSUMER CIRCUIT, PQFP48, 1.40 MM HEIGHT, PLASTIC, TQFP-48

AD9801JCSTRL Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerRochester Electronics
Parts packaging codeQFP
package instruction1.40 MM HEIGHT, PLASTIC, TQFP-48
Contacts48
Reach Compliance Codeunknown
Commercial integrated circuit typesCONSUMER CIRCUIT
JESD-30 codeS-PQFP-G48
JESD-609 codee0
length7 mm
Humidity sensitivity levelNOT SPECIFIED
Number of functions1
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusCOMMERCIAL
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.5 V
Minimum supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width7 mm

AD9801JCSTRL Preview

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FEATURES
10-Bit, 18 MSPS A/D Converter
18 MSPS Full-Speed CDS
Low Noise, Wideband PGA
Internal Voltage Reference
No Missing Codes Guaranteed
+3 V Single Supply Operation
Low Power CMOS: 185 mW
48-Pin TQFP Package
PBLK
19
CCD Signal Processor
For Electronic Cameras
AD9801
FUNCTIONAL BLOCK DIAGRAM
CLPDM
23
PGACONT1 PGACONT2
29
30
SHP SHD ADCCLK
21
22
16
CLAMP
PIN
27
CDS
DIN
26
CLAMP
REFERENCE
37
48
47
18
20
33
TIMING
GENERATOR
PGA
S/H
A/D
10
2
DOUT
11
AD9801
43
17
12
DRVDD
CMLEVEL VRT VRB STBY
CLPOB
ACVDD
ADVDD
DVDD
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9801 is a complete CCD signal processor developed for
electronic cameras. It is well suited for both video conferencing
and consumer level still camera applications.
The signal processing chain is comprised of a high speed CDS,
variable gain PGA and 10-bit ADC. Required clamping
circuitry and an onboard voltage reference are also provided.
The AD9801 operates from a single +3 V supply with a typical
power consumption of 185 mW.
The AD9801 is packaged in a space saving 48-pin thin-quad
flatpack (TQFP) and is specified over an operating temperature
range of 0°C to +70°C.
1. On-Chip Input Clamp and CDS
Clamp circuitry and high speed correlated double sampler
allow for simple ac coupling to interface a CCD sensor at full
18 MSPS conversion rate.
2. On-Chip PGA
The AD9801 includes a low noise, wideband amplifier with
analog variable gain from 0 dB to 31.5 dB (linear in dB).
3. 10-Bit, High Speed A/D Converter
A linear 10-bit ADC is capable of digitizing CCD signals at
the full 18 MSPS conversion rate. (Typical DNL is
±
0.5 LSB
and no missing code performance is guaranteed.)
4. Low Power
At 185 mW, the AD9801 consumes a fraction of the power of
presently available multichip solutions. The part’s power-
down mode (15 mW) further enhances its desirability in low
power, battery operated applications.
5. Digital I/O Functionality
The AD9801 offers three-state digital output control.
6. Small Package
Packaged in a 48-pin, surface-mount thin-quad flatpack, the
AD9801 is well suited to very tight, low headroom designs.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD9801–SPECIFICATIONS
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
(For Functional Operation)
ACVDD
ADVDD
DVDD
DRVDD
POWER SUPPLY CURRENT
ACVDD
ADVDD
DVDD
DRVDD
POWER CONSUMPTION
Normal Operation
Power-Down Mode
MAXIMUM SHP, SHD, ADCCLK RATE
ADC
Resolution
Differential Nonlinearity
No Missing Codes
ADCCLK Rate
Reference Top Voltage
Reference Bottom Voltage
Input Range
CDS
Maximum Input Signal
Pixel Rate
PGA
1
Maximum Gain
High Gain
Medium Gain
Minimum Gain
CLAMP
Average Black Level (During CLPOB. Only
Stable Over PGA Range 0.3 V to 2.7 V)
1
(T
MIN
to T
MAX
with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless
otherwise noted)
Min
0
–65
Typ
Max
70
150
Units
°C
°C
3.00
3.00
3.00
3.00
3.15
3.15
3.15
3.15
39.5
14.6
4.7
0.07
185
15
3.50
3.50
3.50
3.50
V
V
V
V
mA
mA
mA
mA
mW
mW
MHz
Bits
LSB
18
10
±
0.5
GUARANTEED
18
1.75
1.25
1.0
MHz
V
V
V p-p
mV p-p
MHz
dB
dB
dB
dB
500
18
31.5
19
3.5
–1
15
0.5
–5
23
6.5
+3
32
LSB
PGA test conditions: max gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain PGACONT1 =
0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(T
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage
Low Level Output Voltage
MIN
to T
MAX
with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
I
OH
I
OL
Min
2.4
Typ
Max
Units
V
V
µA
µA
pF
V
V
µA
µA
0.6
10
10
10
2.4
0.6
50
50
Specifications subject to change without notice.
–2–
REV. 0
AD9801
TIMING SPECIFICATIONS
(T
Parameter
ADCCLK CLOCK PERIOD
ADCCLK High Level Period
ADCCLK Low Level Period
SHP, SHD Clock Period
Digital Output Delay
MIN
to T
MAX
with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)
Min
55.6
24.8
24.8
55.6
Typ
27.8
27.8
20
Max
Units
ns
ns
ns
ns
ns
Digital Output Data Control
Mode1
0
0
1
1
Mode2
0
1
0
1
Digital Output Data (D9–D0)
Normal Operation
1 0
1 0 1
0 1
0 1 0
High Impedance
0
1
1
0
0
1
1
0
0
1
ABSOLUTE MAXIMUM RATINGS*
Parameter
ADVDD
ACVDD
DVDD
DRVDD
SHP, SHD
ADCCLK, CLOB, CLPDM
PGACONT1, PGACONT2
PIN, DIN
DOUT
VRT, VRB
CLAMP_BIAS
CCDBYP1, CCDBYP2
STBY
MODE1, MODE2
DRVSS, DVSS, ACVSS, ADVSS
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With Respect To
ADVSS, SUBST
ACVSS, SUBST
DVSS, DSUBST
DRVSS, DSUBST
DSUBST
DSUBST
SUBST
SUBST
DSUBST
SUBST
SUBST
SUBST
DSUBST
SUBST
SUBST, DSUBST
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–65
Max
6.5
6.5
6.5
6.5
DVDD + 2.0
DVDD + 0.3
ACVDD + 0.3
ACVDD + 0.3
DRVDD + 0.3
ADVDD + 0.3
ACVDD + 0.3
ACVDD + 0.3
DVDD + 0.3
ADVDD + 0.3
+0.3
+150
+150
+300
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
Model
AD9801
Temperature
0°C to +70°C
Package Description
48-Pin TQFP
Package Option*
ST-48
*ST = Thin Quad Flatpack Package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9801 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD9801
PIN CONFIGURATION
CLAMP_BIAS
PGACONT2
PGACONT1
INT_BIAS1
CCDBYP1
CCDBYP2
24
DVSS
23
CLPDM
22
SHD
21
SHP
20
CLPOB
19
PBLK
18
STBY
17
DVDD
16
ADCCLK
15
DVSS
PIN 1
IDENTIFIER
14
DSUBST
13
DRVSS
1
2
3
4
5
6
7
8
9
10 11 12
ACVDD
ACVDD
ACVDD
ACVSS
36 35 34 33 32 31 30 29 28 27 26 25
CMLEVEL
37
INT_BIAS2
38
MODE2
39
MODE1
40
ADVSS
41
ADVDD
42
ADVDD
43
ADVSS
44
ADVSS
45
SUBST
46
VRB
47
VRT
48
AD9801
TOP VIEW
(Not to Scale)
ADVSS
D1
D2
D3
D4
PIN
D8
(MSB) D9
(LSB) D0
D7
DIN
Pin No.
1
2–11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin Name
ADVSS
D0–D9
DRVDD
DRVSS
DSUBST
DVSS
ADCCLK
DVDD
STBY
PBLK
CLPOB
SHP
SHD
CLPDM
DVSS
CCDBYP2
DIN
PIN
CCDBYP1
PGACONT1
PGACONT2
ACVSS
CLAMP_BIAS
ACVDD
ACVDD
ACVDD
INT_BIAS1
CMLEVEL
INT_BIAS2
MODE2
MODE1
ADVSS
ADVDD
ADVDD
ADVSS
ADVSS
SUBST
VRB
VRT
Type
P
DO
P
P
P
P
DI
P
DI
DI
DI
DI
DI
DI
DI
AO
AI
AI
AO
AI
AI
P
AO
P
AI
AI
AO
AO
AO
DI
DI
P
P
P
P
P
P
AO
AO
Description
Analog Ground
Digital Data Outputs
+3 V Digital Driver Supply
Digital Driver Ground
Digital Substrate
Digital Ground
ADC Sample Clock Input
+3 V Digital Supply
Power down (Active HIGH)
Pixel Blanking (Active LOW)
Black Level Restore Clamp (Active LOW)
Reference Sample Clock Input
Data Sample Clock Input
Input Clamp (Active Low)
Digital Ground
CCD Bypass (Decouple to Analog Ground Through 0.1
µF)
CDS Input (Tie to Pin 27 and AC-Couple to CCD Output Through 0.1
µF)
CDS Input (See Above)
CCD Bypass (Decouple to Analog Ground Through 0.1
µF)
Coarse PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1
µF)
Fine PGA Gain Control (0.3 V–2.7 V Decoupled to Analog Ground Through 0.1
µF)
Analog Ground
Clamp Bias Level (Decouple to Analog Ground Through 0.1
µF)
+3 V Analog Supply
+3 V Analog Supply
+3 V Analog Supply
Internal Bias Level (Decouple to Analog Ground Through 0.1
µF)
Common-Mode Level (Decouple to Analog Ground Through 0.1
µF)
Internal Bias Level (Decouple to Analog Ground Through 0.1
µF)
ADC Test Mode Control (See Digital Output Data Control)
ADC Test Mode Control (See Digital Output Data Control)
Analog Ground
+3 V Analog Supply
+3 V Analog Supply
Analog Ground
Analog Ground
Substrate (Connect to Analog Ground)
Bottom Reference Bypass (Decouple to Analog Ground Through 0.1
µF)
Top Reference Bypass (Decouple to Analog Ground Through 0.1
µF)
–4–
REV. 0
DRVDD
D5
D6
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AD9801JCSTRL Related Products

AD9801JCSTRL AD9801JCST
Description SPECIALTY CONSUMER CIRCUIT, PQFP48, 1.40 MM HEIGHT, PLASTIC, TQFP-48 SPECIALTY CONSUMER CIRCUIT, PQFP48, 1.40 MM HEIGHT, PLASTIC, TQFP-48
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker Rochester Electronics Rochester Electronics
Parts packaging code QFP QFP
package instruction 1.40 MM HEIGHT, PLASTIC, TQFP-48 1.40 MM HEIGHT, PLASTIC, TQFP-48
Contacts 48 48
Reach Compliance Code unknown unknown
Commercial integrated circuit types CONSUMER CIRCUIT CONSUMER CIRCUIT
JESD-30 code S-PQFP-G48 S-PQFP-G48
JESD-609 code e0 e0
length 7 mm 7 mm
Humidity sensitivity level NOT SPECIFIED NOT SPECIFIED
Number of functions 1 1
Number of terminals 48 48
Maximum operating temperature 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LFQFP LFQFP
Package shape SQUARE SQUARE
Package form FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius) NOT SPECIFIED 220
Certification status COMMERCIAL COMMERCIAL
Maximum seat height 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 3.5 V 3.5 V
Minimum supply voltage (Vsup) 3 V 3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface TIN LEAD TIN LEAD
Terminal form GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED 30
width 7 mm 7 mm

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