CD40100BKMSR datasheet, PDF - EEWORLD Datasheet

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CD40100BKMSR: Description32-BIT BIDIRECTIONAL SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16, CERAMIC, FP-16; Categorylogic logic; File Size194KB，9 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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CD40100BKMSR Overview

32-BIT BIDIRECTIONAL SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16, CERAMIC, FP-16

CD40100BKMSR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	DFP
package instruction	DFP, FL16,.3
Contacts	16
Reach Compliance Code	not_compliant
Counting direction	BIDIRECTIONAL
JESD-30 code	R-CDFP-F16
JESD-609 code	e0
Logic integrated circuit type	SERIAL IN SERIAL OUT
Maximum Frequency@Nom-Sup	1000000 Hz
Number of digits	32
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	TRUE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL16,.3
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
propagation delay (tpd)	972 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	2.92 mm
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	100k Rad(Si) V
Trigger type	POSITIVE EDGE
width	6.73 mm
minfmax	0.74 MHz

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CD40100BMS

CMOS 32-Stage Static

Left/Right Shift Register

Description

CD40100BMS is a 32-Stage shift register containing 32

D-type master-slave flip-flops.

The data present at the SHIFT RIGHT INPUT is transferred

into the first register stage synchronously with the positive

CLOCK edge, provided the LEFT/RIGHT CONTROL is at a

low level, the RECIRCULATE CONTROL is at a high level,

and the CLOCK INHIBIT is low. If the LEFT/RIGHT

CONTROL is at a high level and the RECIRCULATE

CONTROL is also high, data at the SHIFT LEFT INPUT is

transferred into the 32nd register stage synchronously with

the positive CLOCK transition, provided the CLOCK INHIBIT

is low. The state of the LEFT/RIGHT CONTROL,

RECIRCULATE CONTROL, and CLOCK INHIBIT should not

be changed when the CLOCK is high.

Data is shifted one stage left or one stage right depending on

the state of the LEFT/RIGHT CONTROL, synchronously with

the positive CLOCK edge. Data clocked into the first or 32nd

RIGHT OUTPUT respectively, on the next negative CLOCK

transition (see Data Transfer Table). No shifting occurs on the

positive CLOCK edge if the CLOCK INHIBIT line is at a high

level. With the RECIRCULATE CONTROL low, data in the

32nd stage is shifted into the first stage when the LEFT/

RIGHT CONTROL is low and from the first stage to the 32nd

stage when the LEFT/RIGHT CONTROL is low, and from the

first state to the 32nd stage when the LEFT/RIGHT control is

high. The CD40100BMS is supplied in these 16-lead outline

packages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4T

H2R

H6W

December 1992

Features

• High Voltage Type (20V Rating)

• Fully Static Operation

• Shift Left/Shift Right Capability

• Multiple Package Cascading

• Recirculate Capability

• LIFO of FIFO Capability

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Standardized, Symmetrical Output Characteristics

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Serial Shift Registers

• Time Delay Circuits

• Expandable N-Bit Data Storage Stack (LIFO Operation)

Pinout

CD40100BMS

TOP VIEW

CLOCK INHIBIT

CLOCK

SHIFT LEFT OUT

SHIFT LEFT IN

VSS

16 VDD

15 NC

14 NC

LEFT/RIGHT

CONTROL

12 SHIFT RIGHT OUT

11 SHIFT RIGHT IN

10 NC

RECIRCULATE

CONTROL

NC = NO CONNECTION

Functional Diagram

LEFT/RIGHT

CONTROL

SHIFT RIGHT

CLOCK

CLOCK INHIBIT

SHIFT LEFT

RECIRCULATE

CONTROL

VSS = 8

VDD = 16

NC = 1, 5, 7, 10, 14, 15

SHIFT LEFT

OUT

SHIFT RIGHT

OUT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

7-1277

FN3349

CD40100BKMSR Related Products

	CD40100BKMSR	CD40100BFMSR	CD40100BDMSR
Description	32-BIT BIDIRECTIONAL SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16, CERAMIC, FP-16	4000/14000/40000 SERIES, 32-BIT BIDIRECTIONAL SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16	32-BIT BIDIRECTIONAL SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, BRAZE SEALED, CERAMIC, DIP-16
Is it Rohs certified?	incompatible	incompatible	incompatible
Parts packaging code	DFP	DIP	DIP
package instruction	DFP, FL16,.3	DIP, DIP16,.3	DIP, DIP16,.3
Contacts	16	16	16
Reach Compliance Code	not_compliant	not_compliant	not_compliant
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
JESD-30 code	R-CDFP-F16	R-GDIP-T16	R-CDIP-T16
JESD-609 code	e0	e0	e0
Logic integrated circuit type	SERIAL IN SERIAL OUT	SERIAL IN SERIAL OUT	SERIAL IN SERIAL OUT
Maximum Frequency@Nom-Sup	1000000 Hz	1000000 Hz	1000000 Hz
Number of digits	32	32	32
Number of functions	1	1	1
Number of terminals	16	16	16
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C
Output polarity	TRUE	TRUE	TRUE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP	DIP	DIP
Encapsulate equivalent code	FL16,.3	DIP16,.3	DIP16,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5/15 V	5/15 V	5/15 V
propagation delay (tpd)	972 ns	972 ns	972 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum seat height	2.92 mm	5.08 mm	5.08 mm
Nominal supply voltage (Vsup)	5 V	5 V	5 V
surface mount	YES	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	FLAT	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	6.73 mm	7.62 mm	7.62 mm
minfmax	0.74 MHz	0.74 MHz	0.74 MHz
Maker	Renesas Electronics Corporation	-	Renesas Electronics Corporation

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