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MTD5P06V
Preferred Device
Power MOSFET
5 Amps, 60 Volts P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
•
Avalanche Energy Specified
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
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V
(BR)DSS
60 V
R
DS(on)
TYP
340 mW
P−Channel
D
I
D
MAX
5.0 A
w
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
G
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
1
1 2
3
4
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage
−
Continuous
−
Non−repetitive (t
p
≤
10 ms)
Drain Current
−
Continuous @ 25°C
Drain Current
−
Continuous @ 100°C
Drain Current
−
Single Pulse (t
p
≤
10
μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C
(Note 2)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc, Peak
I
L
= 5 Apk, L = 10 mH, R
G
= 25
Ω)
Thermal Resistance
−
Junction−to−Case
−
Junction−to−Ambient (Note 1)
−
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 sec
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
60
60
±
15
±
25
5
4
18
40
0.27
2.1
−55
to
175
125
S
MARKING DIAGRAMS
4
Drain
YWW
5P06V
2
1
3
Drain
Gate
Source
4
Drain
YWW
5P06V
1 2 3
Gate Drain Source
Package
DPAK
DPAK
Straight Lead
DPAK
Shipping
75 Units/Rail
75 Units/Rail
2500 Tape & Reel
Publication Order Number:
MTD5P06V/D
I
DM
P
D
DPAK
CASE 369C
Style 2
4
T
J
, T
stg
E
AS
R
θJC
R
θJA
R
θJA
T
L
3.75
100
71.4
260
°C/W
3
DPAK
CASE 369D
Style 2
5P06V
Y
WW
Device Code
= Year
= Work Week
2
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum
recommended pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size.
ORDERING INFORMATION
Device
MTD5P06V
MTD5P06V−1
MTD5P06VT4
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
March, 2006
−
Rev. 5
1
MTD5P06V
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 150°C)
Gate−Body Leakage Current (V
GS
=
±
15 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 2.5 Adc)
Drain−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 5 Adc)
(V
GS
= 10 Vdc, I
D
= 2.5 Adc, T
J
= 150°C)
Forward Transconductance
(V
DS
= 15 Vdc, I
D
= 2.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DD
= 30 Vdc, I
D
= 5 Adc,
V
GS
= 10 Vdc,
R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
(V
DS
= 48 Vdc, I
D
= 5 Adc,
V
GS
= 10 Vdc)
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 5 Adc, V
GS
= 0 Vdc)
(I
S
= 5 Adc, V
GS
= 0 Vdc, T
J
= 150°C)
V
SD
Vdc
−
−
−
−
−
−
1.72
1.34
97
73
24
0.42
3.5
−
−
−
−
−
μC
ns
−
−
−
−
−
−
−
−
11
26
17
19
12
3.0
5.0
5.0
20
50
30
40
20
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
367
140
29
510
200
60
pF
V
GS(th)
Vdc
2.0
−
−
−
−
1.5
2.8
4.7
0.34
−
−
3.6
4.0
−
0.45
2.7
2.6
Mhos
−
mV/°C
Ohm
Vdc
V
(BR)DSS
Vdc
60
−
−
−
−
−
61.2
−
−
−
−
−
10
100
100
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
V
DS(on)
g
FS
Reverse Recovery Time
(I
S
= 5 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs)
Reverse Recovery Stored
Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
t
rr
t
a
t
b
Q
RR
L
D
L
S
nH
−
−
4.5
7.5
−
nH
−
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2
MTD5P06V
TYPICAL ELECTRICAL CHARACTERISTICS
10
V
GS
= 10V
I D , DRAIN CURRENT (AMPS)
8
T
J
= 25°C
6V
9V
10
7V
I D , DRAIN CURRENT (AMPS)
9
8
7
6
5
4
3
2
1
9
0
2
3
4
5
6
7
8
8V
V
DS
≥
10 V
T
J
= −55°C
25°C
100°C
6
4
5V
2
4V
0
0
1
2
3
4
5
6
7
8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
1
2
3
4
5
6
7
I
D
, DRAIN CURRENT (AMPS)
8
9
10
− 55°C
25°C
V
GS
= 10 V
T
J
= 100°C
0.4
T
J
= 25°C
V
GS
= 10 V
0.35
0.3
15 V
0.25
0.2
1
2
3
4
5
7
6
I
D
, DRAIN CURRENT (AMPS)
8
9
10
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
−50
−25
0
25
50
75
100
125
T
J
, JUNCTION TEMPERATURE (°C)
150
175
I DSS , LEAKAGE (nA)
V
GS
= 10 V
I
D
= 2.5 A
100
V
GS
= 0 V
10
T
J
= 125°C
1
0
50
10
20
30
40
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
60
Figure 5. On−Resistance Variation with
Temperature
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3
Figure 6. Drain−To−Source Leakage
Current versus Voltage
MTD5P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1000
900
800
C, CAPACITANCE (pF)
700
600
500
400
300
200
100
0
10
V
GS
= 0 V
5
V
GS
0
V
DS
5
C
rss
10
15
20
25
C
oss
C
iss
C
rss
C
iss
V
DS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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