M463L0914DT0
172pin DDR Micro SODIMM
64MB DDR SDRAM MODULE
(8Mx64 based on 8Mx16 DDR SDRAM)
172pin Micro DIMM
64-bit Non-ECC/Parity
Revision 0.1
Jan. 2002
Rev. 0.0 Dec. 2001
M463L0914DT0
Revision History
Revision 0.0 (Dec. 2001)
1. First release
172pin DDR Micro SODIMM
Revision 0.1 (Jan, 2002)
1. Added tRAP(Active to Read w/ autoprecharge command)
Rev. 0.0 Dec. 2001
M463L0914DT0
M463L0914DT0 172pin DDR Micro DIMM
8Mx64 172pin DDR Micro DIMM based on 8Mx16
GENERAL DESCRIPTION
The Samsung M463L0914DT0 is 8M bit x 64 Double Data
Rate SDRAM high density memory modules.
The Samsung M463L0914DT0 consists of four CMOS 8M x 16
bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 172pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M463L0914DT0 is Dual In-line Memory Modules and
intended for mounting into 172pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
172pin DDR Micro SODIMM
FEATURE
• Performance range
Part No.
Max Freq.
Interface
M463L0914DT0-C(L)B3 166MHz(6ns@CL=2.5)
M463L0914DT0-C(L)A2 133MHz(7.5ns@CL=2)
M463L0914DT0-C(L)B0 133MHz(7.5ns@CL=2.5)
M463L0914DT0-C(L)A0 100MHz(10ns@CL=2)
• Power supply : Vdd: 2.5V
±
0.2V, Vddq: 2.5V
±
0.2V
SSTL_2
•
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK )
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB :
Height 1200 mil,
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
Front
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
V
SS
DQ19
DQ24
V
DD
Pin
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
Front
DQ25
DQS3
V
S S
DQ26
DQ27
V
DD
CKE1
A12
A9
A7
V
S S
A5
A3
A1
A10/AP
V
DD
BA0
WE
S0
A13
V
S S
DQ32
DQ33
V
DD
DQS4
DQ34
V
S S
DQ35
DQ40
Pin
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
Front
V
DD
DQ41
DQS5
V
S S
DQ42
DQ43
V
DD
V
DD
V
S S
V
S S
DQ48
DQ49
V
DD
DQS6
DQ50
V
S S
DQ51
DQ56
V
DD
DQ57
DQS7
V
S S
DQ58
DQ59
V
DD
SDA
SCL
V
D D
SPD
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
Back
V
REF
V
S S
DQ4
DQ5
V
DD
DM0
DQ6
V
S S
DQ7
DQ12
V
DD
DQ13
DM1
V
S S
DQ14
DQ15
V
DD
V
DD
V
S S
V
S S
DQ20
DQ21
V
DD
DM2
DQ22
V
S S
DQ23
DQ28
V
DD
Pin
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
Back
DQ29
DM3
V
S S
DQ30
DQ31
V
DD
CKE0
A11
A8
A6
V
S S
A4
A2
A0
BA1
V
DD
RAS
CAS
S1
RFU
V
S S
DQ36
DQ37
V
DD
DM4
DQ38
V
S S
DQ39
DQ44
Pin
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
Back
V
D D
DQ45
DM5
V
SS
DQ46
DQ47
V
D D
CK1
CK1
V
SS
DQ52
DQ53
V
D D
DM6
DQ54
V
SS
DQ55
DQ60
V
D D
DQ61
DM7
V
SS
DQ62
DQ63
V
D D
SA0
SA1
SA2
PIN DESCRIPTION
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0~ CK1,
CK0 ~ CK1
CKE0
CS0
RAS
CAS
WE
DM0 ~ DM7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
*
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply ( 2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Dec. 2001
M463L0914DT0
FUNCTIONAL BLOCK DIAGRAM
CKE1
S1
CKE0
S0
CS
CKE
CS
CKE
172pin DDR Micro SODIMM
N.C.
N.C.
X pF
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
10
11
12
13
14
15
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Load matching
Capacitors on
Raw card A
A0-AN
RAS
CAS
WE
CKE0
S0
Raw card B
10 pF
10 pF
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS5
DM5
D0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D2
DRAM
CKE
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
CS
CKE
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
MicroDIMM
Connector CK
CK
DRAM
Cap
Cap
Two Loads (Raw card A)
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
DQS7
DM7
D1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CK
D3
CK
Raw card A: 0.5 pF
Raw card B: 1.0 pF
I/O 13
I/O 14
I/O 15
BA0 - BA1
Clock Wiring
Clock
Input
CK0/CK0
CK1/CK1
SDRAMs
2 SDRAMs + 2Caps
2 SDRAMs + 2Caps
A0 - A12
RAS
CAS
CKE0
WE
V
DDSPD
V
D D
/V
DDQ
SPD
D0 - D3
D0 - D3
VREF
V
SS
D0 - D3
D0 - D3
SCL
WP
A0
SA0
A1
SA1
Serial PD
BA0-BA1: DDR SDRAMs D0 - D3
A0-A12: DDR SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
CAS: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
SDA
A2
SA2
Rev. 0.0 Dec. 2001
M463L0914DT0
Absolute Maximum Rate
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
& V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
172pin DDR Micro SODIMM
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
6
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70°C)
Parameter
Supply voltage(for device with a nominal V
DD
of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
Output leakage current
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
+ 0.84V
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
- 0.84V
Output High Current(Half strengh driver)
;V
OUT
= V
TT
+ 0.45V
Output High Current(Half strengh driver)
;V
OUT
= V
TT
- 0.45V
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
I H
(DC)
V
IL
(DC)
V
I N
(DC)
V
I D
(DC)
V
IX
(DC)
I
I
I
O Z
I
OH
I
OL
I
OH
Min
2.3
2.3
VDDQ/2-50mV
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
1.15
-2
-5
-16.8
16.8
-9
Max
2.7
2.7
VDDQ/2+50mV
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.3
V
DDQ
+0.6
1.35
2
5
Unit
Note
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
3
5
1
2
4
4
I
OL
9
mA
Notes
1. Includes
±
25mV margin for DC offset on V
REF
, and a combined total of
±
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
≤
3nH.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.0 Dec. 2001