DATASHEET
LOCO™ PLL CLOCK MULTIPLIER
Description
The ICS502 LOCO
TM
is the most cost effective way to
generate a high-quality, high-frequency clock output and a
reference from a lower frequency crystal or clock input. The
name LOCO stands for Low Cost Oscillator, as it is
designed to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques, the
device uses a standard fundamental mode, inexpensive
crystal to produce output clocks up to 160 MHz.
Stored in the chip’s ROM is the ability to generate six
different multiplication factors, allowing one chip to output
many common frequencies (see table on page 2).
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed. For
applications which require defined input to output skew, use
the ICS570B.
ICS502
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Packaged as 8-pin SOIC or die
Available in Pb (lead) free package
IDT’s lowest cost PLL clock
Zero ppm multiplication error
Easy to cascade with ICS5xx series
Input crystal frequency of 5 – 27 MHz
Input clock frequency of 2 – 50 MHz
Output clock frequencies up to 190 MHz
Low jitter – 50 ps one sigma
Compatible with all popular CPUs
Duty cycle of 45/55 up to 160 MHz
Operating voltages of 3.0 to 5.5 V
25 mA drive capability at TTL levels
Industrial temperature version available
Advanced, low-power CMOS process
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VDD
S1, S0
X1/ICLK
Crystal or
Clock input
X2
2
PLL Clock
Multiplier
Circuitry and
ROM
CLK
Crystal
OScillator
REF
GND
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
1
ICS502
REV L 092209
ICS502
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Clock Decoding Table (MHz)
S1 S0
0
0
1
0
1
0
1
CLK
x2
x5
x3
x3.33
x4
x2.5
X1/ I CLK
VDD
GND
REF
1
2
3
4
8
7
6
5
X2
S1
S0
CLK
0
M
M
1
1
8 Pi n (150 mi l ) SOI C
Minimum input frequency for all selections is per table on
page 3.
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
Input
Selection (S1, S0)
Output
Input
Selection (S1, S0)
20
10
0, 0
64
16
1, 0
25
10
1, 1
66.66
20
M, 1
30
10
M, 0
72
24
M, 0
32
16
0, 0
75
15
0, 1
33.33
10
M, 1
80
20
1, 0
37.5
15
1, 1
81
27
M, 0
40
20
0, 0
90
27
M, 1
48
16
M, 0
100
20
0, 1
50
20
1, 1
108
27
1, 0
54
13.5
1, 0
120
24
0, 1
60
20
M, 0
135
27
0, 1
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI/ICLK
VDD
GND
REF
CLK
S0
S1
X2
Pin
Type
Input
Power
Power
Output
Output
Input
Input
Input
Pin Description
Crystal connection or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Buffered crystal oscillator output clock.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD.
Select 1 for output clock. Connect to GND or VDD or float.
Crystal connection. Leave unconnected for clock input.
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
2
ICS502
REV L 092209
ICS502
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS502
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND. It must be connected close to the
ICS502 to minimize lead inductance. No external power
supply filtering is required for the ICS502.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors, if needed, must be connected from each of the
pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 8 pF [(16-12) x 2] = 8.
Series Termination Resistor
A 33
Ω
terminating resistor can be used next to the CLK pin.
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS502. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (industrial)
Ambient Operating Temperature (commercial)
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85
°
C
0 to +70
°
C
-65 to +150
°
C
260
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3
Typ.
–
–
Max.
+70
+85
+5.5
Units
°
C
°
C
V
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
3
ICS502
REV L 092209
ICS502
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
VDD=5.0 V ±5%
, Ambient temperature -40 to +85
°
C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
IDD Operating Supply Current, 20
MHz crystal
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance, S1, S0, and OE
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IM
V
IL
V
OH
V
OL
Conditions
ICLK (pin 1)
ICLK (pin 1)
OE (pin 7)
OE (pin 7)
S0, S1
S1
S0, S1
I
OH
= -25 mA
I
OL
= 25 mA
No load,
100 MHz
CLK output
Pin 7
Pins 4, 6, 7
Min.
3
(VDD/2)+1
Typ.
Max.
5.5
(VDD/2)-1
Units
V
V
V
V
V
V
V
2
0.8
VDD-0.5
VDD/2
0.5
2.4
0.4
20
+70
270
4
V
V
V
mA
mA
k
Ω
pF
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
4
ICS502
REV L 092209
ICS502
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
AC Electrical Characteristics
VDD = 5.0 V ±5%
, Ambient Temperature -40 to +85
°
C, unless stated otherwise
Parameter
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5V
Output Frequency, VDD = 3.0 to 3.6V
Output Frequency, VDD = 4.5 to 5.5V
Output Frequency, VDD = 3.0 to 3.6V
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
PLL Bandwidth
Output Enable Time, OE high to
output on
Output Disable Time, OE low to
tri-state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Symbol
F
IN
F
IN
F
OUT
F
OUT
t
OR
t
OF
t
OD
Conditions
Min.
5
2
Typ.
Max.
27
50
160
120
190
140
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
0 to +70
°
C
-40 to +85
°
C
+25
°
C
+25
°
C
0.8 to 2.0 V
2.0 to 8.0V
1.5V, up to 160 MHz
14
14
14
14
1
1
45
10
50
50
49-51
55
%
kHz
ns
ns
ps
ps
t
ja
t
js
Deviation from mean
+70
25
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
5
ICS502
REV L 092209
Discrete Device
京公网安备 11010802033920号
EEWORLD
