RF2617
10
Typical Applications
• 3V CDMA/FM Cellular Systems
• Supports Dual-Mode AMPS/CDMA
• Supports Dual-Mode TACS/CDMA
• General Purpose Linear IF Amplifier
• Commercial and Consumer Systems
• Portable Battery Powered Equipment
3V CDMA/FM RECEIVE AGC AMPLIFIER
Product Description
The RF2617 is a complete AGC amplifier designed for
the receive section of 3V dual-mode CDMA/FM cellular
applications. It is designed to amplify IF signals while pro-
viding more than 90dB of gain control range. Noise Fig-
ure, IP
3
, and other specifications are designed to be
compatible with the IS-95 Interim Standard for CDMA cel-
lular communications. This circuit is designed as part of
the RFMD CDMA Chip Set, consisting of a Transmit IF
AGC Amp, a Transmit Upconverter, a Receive LNA/Mixer,
and this Receive IF AGC Amp. The IC is manufactured on
an advanced high frequency Silicon Bipolar process, and
is packaged in a standard miniature 16-lead plastic SSOP
package.
0.157
0.150
0.012
0.008
0.196
0.189
0.025
0.0688
0.0532
-A-
0.0098
0.0040
0.2440
0.2284
8° MAX
0°MIN
0.050
0.016
0.0098
0.0075
NOTES:
1. Shaded lead is Pin 1.
2. All dimensions are excluding mold flash.
3. Lead coplanarity - 0.005 with respect to datum "A".
Optimum Technology Matching® Applied
Si Bi-CMOS
SiGe HBT
Si CMOS
• Supports Dual Mode Operation
CDMA+ 1
CDMA- 2
GND 3
FM+ 4
FM- 5
GND 6
IN SELECT 7
NC 8
IN
SEL.
GAIN
CONTROL
16 GC
15 VCC
14 VCC
13 VCC
12 GND
11 GND
10 OUT+
9 OUT-
• -48dB to +48dB Gain Control Range
• Single 3V Power Supply
• Digitally Selectable Inputs
• -2dBm Input IP
3
• 12MHz to 285MHz Operation
Ordering Information
RF2617
RF2617 PCBA
3V CDMA/FM Receive AGC Amplifier
Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc.
7625 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Rev B4 010717
10-17
IF AMPLIERS
ü
Si BJT
Package Style: SSOP-16
10
GaAs HBT
GaAs MESFET
Features
RF2617
Absolute Maximum Ratings
Parameter
Supply Voltage
Control Voltage
Input RF Power
Operating Ambient Temperature
Storage Temperature
Value
-0.5 to +7.0
-0.5 to +5.0
+10
-40 to +85
-40 to +150
Unit
V
DC
V
DC
dBm
°C
°C
Caution!
ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Parameter
Specification
Min.
Typ.
Max.
Unit
Condition
T=25°C, 85MHz, V
CC
=3.0V, Z
S
=500
Ω,
Z
L
=500Ω, 500Ω External CDMA Input Ter-
minating Resistor, 500Ω External Output
Terminating Resistor (Effective Z
S
=333Ω,
Effective Z
L
=250Ω) (See application sche-
matic).
Overall
Frequency Range
CDMA Maximum Gain
CDMA Minimum Gain
FM Maximum Gain
FM Minimum Gain
Gain Slope
Gain Control Voltage Range
Gain Control Input Impedance
Noise Figure
Input IP
3
+45
+45
10
IF AMPLIERS
Stability (Max VSWR)
-44
-4
10:1
12 to 285
+48
-48
+49
-48
57
0 to 3
30
5
-40
-2
-45
-45
8
MHz
dB
dB
dB
dB
dB/V
V
DC
kΩ
dB
dBm
dBm
V
GC
=2.4V
V
GC
=0.3V
V
GC
=2.4V
V
GC
=0.3V
Measured in 0.5V increments
Source impedance of 4.7kΩ
At maximum gain and 85MHz
At +40dB gain, referenced to 500Ω
At minimum gain, referenced to 500Ω
Spurious<-70dBm
CDMA, differential
FM, single-ended
IF Input
Input Impedance
Input Impedance
CDMA to FM Isolation
1
850
30
2.7 to 3.3
13
14
kΩ
Ω
dB
V
mA
mA
Power Supply
Voltage
Current Consumption
Current Consumption
15
16
Minimum gain, V
CC
=3.0V
Maximum gain, V
CC
=3.0V
10-18
Rev B4 010717
RF2617
Pin
1
Function
CDMA+
Description
CDMA balanced input pin. This pin is internally DC-biased and should
be DC-blocked if connected to a device with a DC level other than V
CC
present. A DC to connection to V
CC
is acceptable. For single-ended
input operation, one pin is used as an input and the other CDMA input
is AC-coupled to ground. The balanced input impedance is 1kΩ, while
the single-ended input impedance is 500Ω.
Same as pin 2, except complementary input.
Ground connection. For best performance, keep traces physically short
and connect immediately to ground plane.
FM balanced input pin. This pin is internally DC-biased and should be
DC-blocked if connected to a device with DC present. For single-ended
input operation, one pin is used as an input and the other FM input is
AC-coupled to ground. The balanced input impedance is 1.7kΩ, while
the single-ended input impedance is 850Ω.
Interface Schematic
BIAS
700
Ω
CDMA+
700
Ω
CDMA-
2
3
4
CDMA-
GND
FM+
See pin 1.
BIAS
650
Ω
FM+
650
Ω
FM-
5
6
7
FM-
GND
IN SELECT
Same as pin 4, except complementary input.
Same as pin 3.
Selects which IF input (CDMA or FM) is used. This is a digitally con-
trolled input. A logic "high" selects the CDMA input amplifier. A logic
"low" selects the FM input amplifier. The threshold voltage is approxi-
mately 1.3V.
No connection pin. This pin is internally biased and should not be con-
nected to any external circuitry, including ground or V
CC
.
See pin 4.
20 kΩ
IN SELECT
8
9
NC
OUT-
10
11
12
13
OUT+
GND
GND
VCC
Same as pin 3.
Same as pin 3.
Supply Voltage pin. External bypassing is required. The trace length
between the pin and the bypass capacitors should be minimized. The
ground side of the bypass capacitors should connect immediately to
ground plane.
Same as pin 13.
Same as pin 13.
Analog gain adjustment for all amplifiers. Valid control ranges are from
0V to 3.0V. Maximum gain is selected with 3.0V. Minimum gain is
selected with 0V. These voltages are only valid for a 4.7kΩ DC source
impedance.
V
CC
14
15
16
VCC
VCC
GC
12.7 kΩ
23.5 kΩ
15 kΩ
Rev B4 010717
10-19
IF AMPLIERS
Balanced output pin. This is an open-collector output, designed to
operate into a 250Ω balanced load. The load sets the operating imped-
OUT+
ance, but an external choke or matching inductor to V
CC
must also be
supplied in order to correctly bias this output. This bias inductor is typi-
cally incorporated in the matching network between the output and next
stage. Because this pin is biased to V
CC
, a DC-blocking capacitor must
be used if the next stage’s input has a DC path to ground.
Same as pin 9, except complementary output.
See pin 9.
OUT-
10
RF2617
Application Schematic
Measurement
Reference Plane
Z
S
=500
Ω
CDMA IF Filter
CDMA+
CDMA-
Z
IN, EFF
=500
Ω
FM IF Filter
FM IN
Z
S, EFF
=333
Ω
1
2
Z
IN
=1 kΩ
3
4
10 nF
IN
SEL.
GAIN
CONTROL
4.7 kΩ
16
15
10 nF
14
10 nF
13
12
11
10
9
Z
LOAD,EFF
=250
Ω
C1
L1
V
CC
Z
LOAD
=500
Ω
OUT+
R2
500
Ω
C2
C2
OUT-
C1
L1
V
CC
Measurement
Reference Plane
GC
R1
1 kΩ
Z
IN
=850
Ω
Z
S
=850
Ω
5
6
C2
IF IN
SELECT
7
NC 8
R1 sets the CDMA balanced input impedance. The effective input impedance is then 500
Ω.
R2 sets the balanced output impedance to 500
Ω.
L1 and C2 serve dual purposes. L1 serves
as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1
and C2 may be chosen to form an impedance matching network of the load impedance is not
500
Ω.
Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit
at the IF when the load impedance is 500
Ω.
10 nF
Z
OUT
=500
Ω
10
IF AMPLIERS
10-20
Rev B4 010717
RF2617
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
L2
390 nH
J1
CDMA
50
Ω µstrip
T1
C3
15 pF
C4
15 pF
50
Ω µstrip
L1
390 nH
C1
10 nF
C2
10 nF
R1
1 kΩ
1
2
GAIN
CONTROL
16
15
IN
SEL.
14
13
12
11
10
9
C12
15 pF
T2
R2
500
Ω
L4
390 nH
C9
10 nF
C11
15 pF
L5
390 nH
P1-3
C10
10 nF
C13
10 nF
C14
10 nF
P1-3
R3
4.7 kΩ
P1-1
J2
FM
C6
10 pF
L3
330 nH
C5
10 nF
3
4
5
C7
10 nF
6
7
C8
10 nF
8
50
Ω µstrip
P2-1
J3
OUT
P1
P1-1
1
2
P1-3
3
GC
GND
VCC
NC
P2-1
P2
1
2
3
SELECT
GND
2617400-
10
IF AMPLIERS
Rev B4 010717
10-21
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