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Datasheet> All Categories > logic> logic> IDT74ALVCH16841PF
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IDT74ALVCH16841PF

Description
Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56
Categorylogic    logic   
File Size116KB，6 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT74ALVCH16841PF Overview

Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56

IDT74ALVCH16841PF Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionTSSOP, TSSOP56,.25,16
Contacts56
Reach Compliance Codenot_compliant
seriesALVC/VCX/A
JESD-30 codeR-PDSO-G56
JESD-609 codee0
length11.3 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits10
Number of functions2
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP56,.25,16
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply3.3 V
Prop。Delay @ Nom-Sup3.8 ns
propagation delay (tpd)5.1 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.4 mm
Terminal locationDUAL
width4.4 mm

IDT74ALVCH16841PF Preview

IDT74ALVCH16841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT BUS-
INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
Extended commercial range of – 40°C to + 85°C
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
IDT74ALVCH16841
specifically for driving highly capacitive relatively low-impedance loads.
This device is particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The ALVCH16841 can be used as two 10-bit latches or one 20-bit latch.
The 20 latches are transparent D-type latches. The device has noninverting
data (D) inputs and provides true data at its outputs. While the latch-enable
(1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch
follow the D inputs. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the
outputs of the corresponding 10-bit latch in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
OE
does not
affect the internal operation of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The ALVCH16841 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16841 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
Drive Features for ALVCH16841:
– High Output Drivers: ±24mA
– Suitable for heavy loads
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 20-bit interface D-type latch is built using advanced dual metal
CMOS technology. The ALVCH16841 features 3-state outputs designed
Functional Block Diagram
1
OE
1
2
OE
28
1
LE
56
2
LE
29
1
D
1
55
1
D
2
D
1
42
1
D
Q
C
1
2
1
Q
1
Q
C
1
15
2
Q
1
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4699/1
IDT74ALVCH16841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
Q
1
1
Q
2
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
56
55
54
53
52
51
50
49
48
47
46
45
1
LE
1
D
1
1
D
2
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GN D
1
Q
3
1
Q
4
GN D
1
D
3
1
D
4
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
V
CC
1
Q
5
1
Q
6
1
Q
7
V
CC
1
D
5
1
D
6
1
D
7
GN D
1
Q
8
1
Q
9
1
Q
10
2
Q
1
2
Q
2
2
Q
3
GN D
1
D
8
1
D
9
1
D
10
2
D
1
2
D
2
2
D
3
44
SO56-1
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
GN D
2
Q
4
2
Q
5
2
Q
6
GN D
2
D
4
2
D
5
2
D
6
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
NOTE:
1. As applicable to the device type.
GN D
2
Q
9
2
Q
10
2
OE
GN D
2
D
9
2
D
10
2
LE
FUNCTION TABLE
(each 10-bit latch)
(1)
xDx
H
L
X
X
Inputs
xLE
H
H
L
X
xOE
L
L
L
H
Outputs
xQx
H
L
Q
0
Z
SSOP/
TSSOP/TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xDx
xLE
xOE
xQx
Description
Data Inputs
(1)
Latch Enable Inputs (Active HIGH)
Output Enable Inputs (Active LOW)
3-State Outputs
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
Q
0
= Level of Q before the indicated steady-state input conditions were
established.
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74ALVCH16841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH16841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
Parameter
C
PD
Power Dissipation Capacitance
Outputs enabled
C
PD
Power Dissipation Capacitance
Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
12
1
V
CC
= 3.3V ± 0.3V
Typical
20
3
Unit
pF
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xDx to xQx
Propagation Delay
xLE to xQx
Output Enable Time
xOE to xQx
Output Disable Time
xOE to xQx
Setup Time, data before LE↓
Hold Time, data after LE↓
Pulse Duration, LE HIGH
Output skew
(2)
Min.
1
1
1
1.1
0.9
1.2
3.3
—
Max.
5
5.6
6.2
5.3
—
—
—
—
Min.
—
—
—
—
0.7
1.5
3.3
—
V
CC
= 2.7V
Max.
4.7
5.1
6
4.3
—
—
—
—
V
CC
= 3.3V ± 0.3V
Min.
1.2
1
1
1.3
1.1
1.1
3.3
—
Max.
3.9
4.3
4.9
4.1
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH16841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
NEW16link
SAM E PHAS E
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORM ALLY
CLOSE D
LOW
t
PZH
OUTPUT
SW ITCH
NORM ALLY
OPEN
HIGH
V
LOAD /2
V
T
t
PH Z
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD /2
V
LZ
V
OL
V
OH
V
HZ
0V
V
LOAD
Open
GND
V
IN
D.U.T.
V
OU T
R
T
500
Ω
C
L
ALV C Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALV C Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
NEW16link
t
R EM
GND
Open
TSK
t
S U
t
H
OUTPUT SKEW -
INPUT
(x)
t
PH L1
V
IH
V
T
0V
V
OH
t
PLH1
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALV C Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PH L2
-
t
P HL1
ALV C Link
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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