PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4442163-Y, 4442183-Y, 4442323-Y, 4442363-Y
4M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
DOUBLE CYCLE DESELECT
Description
The
µ
PD4442163-Y is a 262,144-word by 16-bit, the
µ
PD4442183-Y is a 262,144-word by 18-bit,
µ
PD4442323-Y is
a 131,072-word by 32-bit and the
µ
PD4442363-Y is a 131,072-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
µ
PD4442163-Y,
µ
PD4442183-Y,
µ
PD4442323-Y and
µ
PD4442363-Y integrates unique synchronous peripheral
circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive
edge of the single clock input (CLK).
The
µ
PD4442163-Y,
µ
PD4442183-Y,
µ
PD4442323-Y and
µ
PD4442363-Y are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer
memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State
(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes
normal operation.
The
µ
PD4442163-Y,
µ
PD4442183-Y,
µ
PD4442323-Y and
µ
PD4442363-Y are packaged in 100-pin PLASTIC LQFP
with a 1.4 mm package thickness for high density and low capacitive loading.
Features
•
3.3 V power supply
•
Synchronous operation
•
Extended operating temperature (T
A
= –40 to +85 °C)
•
Internally self-timed write control
•
Burst read / write : Interleaved burst and linear burst sequence
•
Fully registered inputs and outputs for pipelined operation
•
Double-Cycle deselect timing
•
All registers triggered off positive clock edge
•
3.3 V LVTTL Compatible : All inputs and outputs
•
Fast clock access time : 2.5 ns (250 MHz), 2.8 ns (225 MHz), 3.0 ns (200 MHz), 3.5 ns (167 MHz)
•
Asynchronous output enable : /G
•
Burst sequence selectable : MODE
•
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
•
Separate byte write enable : /BW1 - /BW4 (
µ
PD4442323-Y,
µ
PD4442363-Y), /BW1 - /BW2 (
µ
PD4442163-Y,
µ
PD4442183-Y), /BWE
Global write enable : /GW
•
Three chip enables for easy depth expansion
•
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15463EJ1V0DS00 (1st edition)
Date Published May 2001 NS CP(K)
Printed in Japan
©
2001
µ
PD4442163-Y, 4442183-Y, 4442323-Y, 4442363-Y
Ordering Information
Part number
Access
Time
ns
Clock
Frequency
MHz
250
225
200
167
250
225
200
167
250
225
200
167
250
225
200
167
Core Supply
Voltage
V
3.3 ± 0.165
I/O
Interface
V
3.3
LVTTL
100-pin PLASTIC
LQFP (14
×
20)
Package
µ
PD4442163GF-A40Y
µ
PD4442163GF-A44Y
µ
PD4442163GF-A50Y
µ
PD4442163GF-A60Y
µ
PD4442183GF-A40Y
µ
PD4442183GF-A44Y
µ
PD4442183GF-A50Y
µ
PD4442183GF-A60Y
µ
PD4442323GF-A40Y
µ
PD4442323GF-A44Y
µ
PD4442323GF-A50Y
µ
PD4442323GF-A60Y
µ
PD4442363GF-A40Y
µ
PD4442363GF-A44Y
µ
PD4442363GF-A50Y
µ
PD4442363GF-A60Y
2.5
2.8
3.0
3.5
2.5
2.8
3.0
3.5
2.5
2.8
3.0
3.5
2.5
2.8
3.0
3.5
2
Preliminary Data Sheet M15463EJ1V0DS
µ
PD4442163-Y, 4442183-Y, 4442323-Y, 4442363-Y
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-pin PLASTIC LQFP (14
×
20)
[
µ
PD4442163GF-Y,
µ
PD4442183GF-Y ]
/BWE
/BW2
/BW1
/ADV
/CE2
/GW
CLK
CE2
V
DD
V
SS
/CE
/AC
/AP
NC
NC
A6
A7
A8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
Remark
Refer to
Package Drawing
for 1-pin index mark.
A16
V
SS
A9
/G
Preliminary Data Sheet M15463EJ1V0DS
3
µ
PD4442163-Y, 4442183-Y, 4442323-Y, 4442363-Y
Pin Identifications
[
µ
PD4442163GF-Y,
µ
PD4442183GF-Y ]
Symbol
A0 - A17
Pin No.
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, Synchronous Address Input
44, 45, 46, 47, 48, 49, 50, 80
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, Synchronous Data In,
13, 18, 19, 22, 23
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
I/OP1, NC
Note
I/OP2, NC
Note
/ADV
/AP
/AC
/CE, CE2, /CE2
/BW1, /BW2, /BWE
/GW
/G
CLK
MODE
74
24
83
84
85
98, 97, 92
93, 94, 87
88
86
89
31
ZZ
V
DD
V
SS
V
DD
Q
V
SS
Q
NC
64
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Asynchronous Power Down State Input
Power Supply
Ground
Output Buffer Power Supply
Output Buffer Ground
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, No Connection
39, 42, 43, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Note
NC (No Connection) is used in the
µ
PD4442163GF-Y.
I/OP1 - I/OP2 are used in the
µ
PD4442183GF-Y.
4
Preliminary Data Sheet M15463EJ1V0DS
µ
PD4442163-Y, 4442183-Y, 4442323-Y, 4442363-Y
100-pin PLASTIC LQFP (14
×
20)
[
µ
PD4442323GF-Y,
µ
PD4442363GF-Y ]
/BWE
/BW4
/BW3
/BW2
/BW1
/ADV
/CE2
/GW
CLK
CE2
V
DD
V
SS
/CE
/AC
/AP
A6
A7
A8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
DD
V
SS
NC
NC
A10
A11
A12
A13
A14
A15
Remark
Refer to
Package Drawing
for 1-pin index mark.
A16
A9
/G
Preliminary Data Sheet M15463EJ1V0DS
5
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