HT46R64/HT46C64
A/D with LCD Type 8-Bit MCU
Technical Document
·
Tools Information
·
FAQs
·
Application Note
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
-
HA0004E HT48 & HT46 MCU UART Software Implementation Method
-
HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
-
HA0047E An PWM application example using the HT46 series of MCUs
Features
·
Operating voltage:
·
Watchdog Timer
·
Buzzer output
·
On-chip crystal, RC and 32768Hz crystal oscillator
·
HALT function and wake-up feature reduce power
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
·
24 bidirectional I/O lines
·
Two external interrupt input
·
One 8-bit and one 16-bit programmable timer/event
consumption
·
8-level subroutine nesting
·
8 channels 10-bit resolution A/D converter
·
4-channel 8-bit PWM output shared with 4 I/O lines
·
Bit manipulation instruction
·
16-bit table read instruction
·
Up to 0.5ms instruction cycle with 8MHz system clock
·
63 powerful instructions
·
All instructions in 1 or 2 machine cycles
·
Low voltage reset/detector function
·
52-pin QFP, 56-pin SSOP, 100-pin QFP packages
counter with PFD (programmable frequency divider)
function
·
LCD driver with 33´3 or 32´4 segments
(logical output option for SEG0~SEG15)
·
4K´15 program memory
·
192´8 data memory RAM
·
Supports PFD for sound generation
·
Real Time Clock (RTC)
·
8-bit prescaler for RTC
General Description
The HT46R64/HT46C64 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface di-
rectly to analog signals and which require LCD Inter-
face. The mask version HT46C64 is fully pin and
functionally compatible with the OTP version HT46R64
device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications re-
quiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
Rev. 1.80
1
February 14, 2006
HT46R64/HT46C64
Block Diagram
In te rru p t
C ir c u it
P ro g ra m
E P R O M
P ro g ra m
C o u n te r
S T A C K
IN T C
T M R 0 C
T M R 0
P F D 0
T M R 1 C
T M R 1
P F D 1
M
M
U
P r e s c a le r
X
P D 6 /T M R 0
P D 7 /T M R 1
f
S Y S
/4
X
3 2 7 6 8 H z
f
S
Y S
U
In s tr u c tio n
R e g is te r
M P
M
U
R T C
X
D A T A
M e m o ry
W D T
T im e B a s e
M
U
X
f
S
Y S
/4
R T C
O S C
O S C 3
O S C 4
W D T O S C
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e r a tio n
M U X
P W
P D C
S T A T U S
P D
M
P O R T D
S h ifte r
8 -C h a n n e l
A /D C o n v e rte r
B P
P B C
P B
L C D
M e m o ry
L C D D R IV E R
P O R T B
P D
P D
P D
P D
P D
0 /
4 /
5 /
6 /
7 /
P W
IN
IN
T M
T M
M 0 ~ P D 3 /P W
T 0
T 1
R 0
R 1
M 3
O S C 2
O S C 4
O S
R E
V D
V S
O S
S
D
S
C 1
A C C
P B 0 /A N 0 ~ P B 7 /A N 7
P A 0
P A 1
P A 2
P A 3
P A 4
/B Z
/B Z
/P F D
~ P A 7
C 3
P A C
P A
H A L T
P O R T A
E N /D IS
C O M 0 ~
C O M 2
C O M 3 /
S E G 3 2
S E G 0 ~
S E G 3 1
L V D /L V R
Rev. 1.80
2
February 14, 2006
HT46R64/HT46C64
Pin Assignment
S E G
N
N
N
N
N
N
N
N
O S C
O S C
V D
O S C
O S C
R E
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A
P A 0 /B Z
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
P A 1 /B Z
P A 2
P A 3 /P F D
P A 4
P A 5
P A 6
P A 7
P B 0 /A N 0
P B 1 /A N 1
P B 2 /A N 2
P B 3 /A N 3
P B 4 /A N 4
P B 5 /A N 5
V S S
P D 0 /P W M 0
P D 1 /P W M 1
P D 2 /P W M 2
P D 4 /IN T 0
P D 5 /IN T 1
P D 6 /T M R 0
V L C D
V M A X
V 1
V 2
C 1
C 2
C O M 0
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
R E S
O S C 1
O S C 2
V D D
O S C 3
O S C 4
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
P
P
P
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
C O M 3 /S E G 3 2
C O M 2
C O M 1
P
P
P
P A
N
N
N
N
N
C
C
3
5
1
2
4
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1
D
D
S
Z
Z
0
4
2
1
8 0
7 9
7 8
7 7
C
C
C
C
C
C
C
C
2
S E G
S E G
S E G
N C
N C
N C
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
N C
N C
N C
N C
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
1
3
4
C
C
5
7 6
P A 6
P A 7
P B 0 /A N 0
P B 1 /A N 1
P B 2 /A N 2
P B 3 /A N 3
P B 4 /A N 4
P B 5 /A N 5
P B 6 /A N 6
P B 7 /A N 7
V S S
D 0 /P W M 0
D 1 /P W M 1
D 2 /P W M 2
D 3 /P W M 3
P D 4 /IN T 0
P D 5 /IN T 1
D 6 /T M R 0
D 7 /T M R 1
N C
N C
N C
N C
N C
7
8
9
C
6
7 5
7 4
7 3
7 2
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
7 1
7 0
6 9
6 8
6 7
H T 4 6 R 6 4 /H T 4 6 C 6 4
1 0 0 Q F P -A
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C 2
C 1
V 2
V 1
V M A
V L C
D
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 /S E G 3 2
X
H T 4 6 R 6 4 /H T 4 6 C 6 4
5 6 S S O P -A
0
1
2
S E G 1
S E G
O S C
O S C
V D
O S C
O S C
R E
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
2
3
4
5
D
D
S
Z
Z
4
3
2
1
0
9
2
4
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
P B
P B
P B
P B
P B
P B
1
P D 0 /P
P D 1 /P
P D 2 /P
0
2
3
4
5
P A
P A
P A
/A N
/A N
/A N
/A N
/A N
/A N
V S
W M
W M
W M
S
7
0
1
2
3
4
5
6
5
3 9
3 8
3 7
3 6
3 5
6
7
8
9
1 0
1 1
H T 4 6 R 6 4 /H T 4 6 C 6 4
5 2 Q F P -A
0
1
2
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
S E
S E
S E
C O
C O
C O
C O
V 1
V M
V L
P D
P D
P D
A X
C D
6 /T M R 0
5 /IN T 1
4 /IN T 0
G 2
G 2
G 2
M 3
6
5
4
/S E G 3 2
M 0
M 1
M 2
Note:
The 52-pin QFP package does not support the charge pump (C type bias) of the LCD. The LCD bias type must
select the R type by option.
3
February 14, 2006
Rev. 1.80
HT46R64/HT46C64
Pin Description
Pin Name
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PD0/PWM0
PD1/PWM1
PD2/PWM2
PD3/PWM3
PD4/INT0
PD5/INT1
PD6/TMR0
PD7/TMR1
VSS
VLCD
VMAX
V1, V2, C1, C2
COM0~COM2
COM3/SEG32
SEG0~SEG31
I/O
Options
Wake-up
Pull-high
Buzzer
PFD
Description
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up in-
put by option. Software instructions determine the CMOS output or Schmitt
Trigger input with or without pull-high resistor (determined by pull-high op-
tions: bit option). The BZ, BZ and PFD are pin-shared with PA0, PA1 and
PA3, respectively.
I/O
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
mined by pull-high option: bit option) or A/D input. Once a PB line is selected
as an A/D input (by using software control), the I/O function and pull-high re-
sistor are disabled automatically.
I/O
Pull-high
PWM
Bidirectional 4-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (deter-
mined by pull-high option: bit option). The PWM0/PWM1/PWM2/PWM3 out-
put function are pin-shared with PD0/PD1/PD2/PD3 (dependent on PWM
options).
Bidirectional 4-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (deter-
mined by pull-high option: bit option). The INT0, INT1, TMR0 and TMR1 are
pin-shared with PD4/PD5/PD6/PD7.
Negative power supply, ground
LCD power supply
IC maximum voltage connect to VDD, VLCD or V1
Voltage pump
SEG32 can be set as a segment or as a common output driver for LCD panel
by options. COM0~COM2 are outputs for LCD panel plate.
LCD driver outputs for LCD panel segments. SEG0~SEG23 can be optioned
as logical outputs.
OSC1 and OSC2 are connected to an RC network or a crystal (by options) for
the internal system clock. In the case of RC operation, OSC2 is the output ter-
minal for 1/4 system clock. The system clock may come from the RTC oscilla-
tor. If the system clock comes from RTCOSC, these two pins can be floating.
Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purposes or to a system clock source (depending
on the options). No built-in capacitor
Positive power supply
Schmitt trigger reset input, active low
I/O
Pull-high
¾
I
I
I
O
O
¾
¾
¾
¾
1/3 or 1/4 Duty
Logical Output
OSC1
OSC2
I
O
Crystal or RC
OSC3
OSC4
VDD
RES
I
O
¾
I
RTC or
System Clock
¾
¾
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+6.0V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 1.80
4
February 14, 2006
HT46R64/HT46C64
D.C. Characteristics
Test Conditions
Symbol
Parameter
V
DD
V
DD
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(Crystal OSC, RC OSC)
Operating Current
(f
SYS
=32768Hz)
Standby Current
(*f
S
=T1)
Standby Current
(*f
S
=RTC OSC)
Standby Current
(*f
S
=WDT OSC)
¾
¾
3V
5V
5V
3V
No load, ADC Off
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
¾
¾
¾
¾
¾
¾
3V
5V
3V
5V
V
OH
=0.9V
DD
V
OL
=0.1V
DD
No load, system HALT,
LCD Off at HALT
No load, system HALT,
LCD On at HALT, C type
No load, system HALT,
LCD On at HALT, C type
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VL
CD
=V
DD
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VL
CD
=V
DD
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VL
CD
=V
DD
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VL
CD
=V
DD
(Low bias current option)
¾
¾
¾
¾
¾
¾
Conditions
f
SYS
=4MHz
f
SYS
=8MHz
No load, ADC Off,
f
SYS
=4MHz
No load, ADC Off,
f
SYS
=8MHz
2.2
3.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
0.7V
DD
0
0.9V
DD
2.7
3.0
6
10
-2
-5
¾
¾
1
3
4
0.3
0.6
¾
¾
2.5
10
2
6
17
34
13
28
14
26
10
19
¾
¾
¾
¾
3.0
3.3
12
25
-4
-8
5.5
5.5
2
5
8
0.6
1
1
2
5
20
5
10
30
60
25
50
25
50
20
40
0.3V
DD
V
DD
0.4V
DD
V
DD
3.3
3.6
¾
¾
¾
¾
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
mA
mA
mA
mA
Min.
Typ.
Max.
Unit
Ta=25°C
I
DD1
I
DD2
I
DD3
I
STB1
I
STB2
I
STB3
I
STB4
Standby Current
(*f
S
=RTC OSC)
I
STB5
Standby Current
(*f
S
=RTC OSC)
I
STB6
Standby Current
(*f
S
=WDT OSC)
I
STB7
Standby Current
(*f
S
=WDT OSC)
Input Low Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1
Input High Voltage for I/O Ports,
TMR0, TMR1, INT0 and INT1
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
Low Voltage Detector Voltage
I/O Port Segment Logic Output
Sink Current
I/O Port Segment Logic Output
Source Current
V
IL1
V
IH1
V
IL2
V
IH2
V
LVR
V
LVD
I
OL1
I
OH1
Rev. 1.80
5
February 14, 2006
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