U632H16
PowerStore
2K x 8 nvSRAM
Features
auto matically on power up. The
U632H16 combines the high perfor-
mance and ease of use of a fast
High-performance CMOS no n-
SRAM with n onvolatile data inte-
volatile stati c RAM 2048 x 8 bits
grit y.
Description
25, 35 and 45 ns Ac cess Times
STORE cycles also may be initiated
12, 20 and 25 ns Output Enable
under us er contro l via a softw are
Access Times
The U632H16 has two separate
sequence or via a single pin (HSB).
I
CC
= 15 mA at 200 ns Cy cle
modes of o peration: SRAM mode
Once a STORE cy cle is init iated,
Time
and no nv olatile mode. In SRAM
furt her input or outpu t are disabled
Auto matic S TORE to EEPROM
mode, the memo ry operates as an
until the cycle is co mpleted.
on Po wer Do wn usi ng external
ordinary st atic RA M. In nonvolatile
Because a sequence of addresses
capacito r
operation, data is trans ferred in
is used for STORE initiation, it is
Hardware o r So ftware initiated
parallel fro m SRAM to EEPROM or
imp ortant that no o ther read o r write
STORE
fro m EEPROM to SRAM. In this
access es interv ene in the sequence
(STORE Cy cle Time < 10 ms )
mode SRAM fu nctio ns are disab-
or the sequence will be abo rted.
Auto matic S TORE Timing
led.
RECALL cycles may also be initia-
5
STORE cycles to EEPROM
10
The U632H16 is a fast s tatic RAM
ted by a software sequence.
10 years data retentio n in
(25, 35, 45 ns), w ith a nonvolatile
Internally, RECALL is a two step
EEPROM
electr ically
erasable
PROM
Auto matic RECALL on Po wer Up (EEPROM) element inco rpo rated procedure. First, the SRAM data is
cleared and seco nd, the nonvolatile
Sof tware RECALL I nitiatio n
in each static m emory cell. The
information is tr ans ferred into the
(RECALL Cy cle Time < 20
µs)
SRAM can be read and wri tten an
SRAM cells.
Unlimited RECALL cy cles from
unlimited number of ti mes, while
The RECALL operation in no way
EEPROM
independent nonvolatile data resi-
alters the data in the EEPROM
Single 5 V
±
10 % Operation
des in EEPROM. Data trans fers
cells. The no nvolatile data can be
Operating temperature rang es:
fro m the SRAM to the EEPROM
recalled an unlimited nu mber of
0 to 70
°C
(the STORE operatio n) take place
times.
-40 to 85
°C
auto matically upo n power do wn
CECC 90000 Quality Standard
usi ng charge stored in an external
ESD ch aracteri zatio n according 100
µF
capaci tor. Trans fers fro m
MIL STD 883C M3015.7-HBM
the EEPROM to the SRAM (the
(classific atio n see IC Code Num- RECALL operation) take place
bers)
F
Packages:
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
PDIP28 (300 mil)
PDIP28 (600 mi)
SOP28 (300 mil)
Pin Configuration
VCAP
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
28
27
26
25
24
23
VCCX
W
HSB
A8
A9
n.c .
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Addres s Inputs
Data In/Out
Chip En able
Output Enable
Write Enable
Power Supp ly Volt age
Ground
Capacit or
Hardware Controlle d Store/Busy
22
7
SOP
21
8
9
20
10
19
11
18
12
13
14
17
16
15
PDIP
Top View
December 12, 1997
1
U632H16
Block Diagram
EEPROM Array
32 x (64 x 8)
STORE
Row Decoder
A5
A6
A7
A8
A9
SRAM
Array
32 Rows x
64 x 8 Columns
Store/
Recall
Control
V
CCX
V
SS
V
CAP
Power
Control
RECALL
V
CCX
V
CAP
HSB
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Input Buffers
Column I/O
Column Decoder
Software
Detect
A0 - A10
A0 A1 A2 A3 A4 A10
G
E
W
Truth Table for SRAM Operations
Operating Mode
Standby/not selected
Internal Read
Read
Write
*
H or L
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as input levels of V
IL
= 0 V
and V
IH
= 3 V. The timing reference level of all input and outputsignals is 1.5 V, with the exception of the t
dis
-times and t
en
-times, in which cases
transition is measured
±
200 mV from steady-state voltage.
E
H
L
L
L
HSB
H
H
H
H
W
*
H
H
L
G
*
H
L
*
DQ0 - DQ7
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
Absolute Maximum Ratings
a
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
a:
Symbol
V
CC
V
I
VO
P
D
C-Type
K-Type
T
a
T
stg
Min.
-0.5
-0.3
-0.3
Max.
7
V
CC
+0.5
V
CC
+0.5
1
Unit
V
V
V
W
°C
°C
°C
0
-40
-65
70
85
150
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
December 12, 1997
U632H16
Recommended
Operating Conditions
Power Supply Voltage
b
Input Low Voltage
Input High Voltage
Symbol
V
CC
V
IL
V
IH
-2 V at Pulse Width
10 ns permitted
Conditions
Min.
4.5
-0.3
2.2
Max.
5.5
0.8
V
CC
+0.3
Unit
V
V
V
C-Type
DC Characteristics
Operating Supply Current
c
Symbol
I
CC1
V
CC
V
IL
V
IH
t
c
t
c
t
c
Average Supply Current during
STORE
c
I
CC2
V
CC
E
W
V
IL
V
IH
V
CC
V
IL
V
IH
V
CC
E
t
c
t
c
t
c
Operating Supply Current
at t
cR
= 200 ns
c
(Cycling CMOS Input Levels)
Standby Supply Current
d
(Stable CMOS Input Levels)
I
CC3
V
CC
W
V
IL
V
IH
V
CC
E
V
IL
V
IH
Conditions
Min.
= 5.5 V
= 0.8 V
= 2.2 V
= 25 ns
= 35 ns
= 45 ns
= 5.5 V
≤
0.2 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 4.5 V
= 0.2 V
≥
V
CC
-0.2 V
= 5.5 V
= V
IH
= 25 ns
= 35 ns
= 45 ns
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
= 5.5 V
≥
V
CC
-0.2 V
≤
0.2 V
≥
V
CC
-0.2 V
30
23
20
15
90
80
75
6
Max.
K-Type
Unit
Min.
Max.
95
85
80
7
mA
mA
mA
mA
Average Supply Current during
PowerStore
Cycle
Standby Supply Current
d
(Cycling TTL Input Levels)
I
CC4
4
4
mA
I
CC(SB)1
34
27
23
15
mA
mA
mA
mA
I
CC(SB)
3
3
mA
b:
V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is con-
nected to ground.
c: I
CC1
and I
CC3
are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current I
CC1
is measured for WRITE/READ - ratio of 1/2.
I
CC2
is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table.The current I
CC(SB)1
is measured for WRITE/READ - ratio of 1/2.
December 12, 1997
3
U632H16
C-Type
DC Characteristics
Symbol
V
CC
I
OH
I
OL
V
CC
V
OH
V
OL
V
CC
High
Low
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
I
IH
I
IL
V
IH
V
IL
V
CC
V
OH
V
OL
Conditions
Min.
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
V
OH
V
OL
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0V
= 5.5 V
= 5.5 V
= 0V
1
-1
-1
1
µA
µA
1
-1
-1
1
µA
µA
2.4
0.4
-4
8
8
Max.
Min.
2.4
0.4
-4
Max.
V
V
mA
mA
K-Type
Unit
SRAM MEMORY OPERATIONS
Symbol
Alt.
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
ELQX
t
GLQX
t
AXQX
t
ELICCH
t
EHICCL
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
5
0
3
0
25
25
Min.
25
25
25
12
13
13
5
0
3
0
35
Max.
35
Min. Max.
35
35
35
20
17
17
5
0
3
0
45
Min.
45
45
45
25
20
20
45
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No.
1
2
3
4
5
6
7
8
9
Switching Characteristics
Read Cycle
Read Cycle Time
f
Address Access Time to Data Valid
g
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Z
h
G HIGH to Output in High-Z
h
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time after Address Change
10 Chip Enable to Power Active
e
11 Chip Disable to Power Standby
d, e
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both LOW.
Address valid prior to or coincident with E transition LOW.
Measured
±
200 mV from steady state output voltage.
4
December 12, 1997
U632H16
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
1
t
cR
Ai
Address Valid
2
t
a(A
)
Previos
Data Valid
9
t
v(A )
DQi
Output
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
Output Data
Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
1
t
cR
Ai
Address Valid
2
t
a(A )
11
t
PD
5
t
dis(E)
3
E
G
7
t
en(E)
t
a(E)
4
t
a(G)
DQi
Output
High Impedance
8
t
en(G)
10
t
PU
6
t
dis(G)
AAAAAAAAAAAA
Output Data
AAAAAAAAAAAA
AAAAAAAAAAAA
Valid
AAAAAAAAAAAA
I
CC
ACTIVE
STANDBY
No.
Switching Characteristics
Write Cycle
Symbol
Alt. #1 Alt. #2
t
AVAV
t
WLWH
t
WLEH
t
AVWL
t
AVWH
t
ELWH
t
ELEH
t
DVWH
t
WHDX
t
WHAX
t
WLQZ
t
WHQX
t
DVEH
t
EHDX
t
EHAX
t
AVEL
t
AVEH
t
AVAV
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
5
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
25
20
20
0
20
20
20
12
0
0
10
5
35
30
30
0
30
30
30
18
0
0
13
5
45
35
35
0
35
35
35
20
0
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z
December 12, 1997
5
stm32/stm8
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