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Datasheet> All Categories > Programmable logic devices> Programmable logic> TIBPAL20R8-5CJT
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TIBPAL20R8-5CJT

Description
OT PLD, 7ns, TTL, CDIP24, CERAMIC, DIP-24
CategoryProgrammable logic devices    Programmable logic   
File Size321KB，32 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric Compare View All

TIBPAL20R8-5CJT Overview

OT PLD, 7ns, TTL, CDIP24, CERAMIC, DIP-24

TIBPAL20R8-5CJT Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionDIP,
Reach Compliance Codeunknown
Other featuresREGISTER PRELOAD; POWER-UP RESET
maximum clock frequency111 MHz
JESD-30 codeR-GDIP-T24
JESD-609 codee0
Dedicated input times12
Number of I/O lines
Number of terminals24
Maximum operating temperature75 °C
Minimum operating temperature
organize12 DEDICATED INPUTS, 0 I/O
Output functionREGISTERED
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Programmable logic typeOT PLD
propagation delay7 ns
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal locationDUAL

TIBPAL20R8-5CJT Preview

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE
IMPACT-X
™
PAL
®
CIRCUITS
•
High-Performance Operation:
f
max
(no feedback)
TIBPAL20R’ -5C Series . . . 125 MHz Min
TIBPAL20R’ -7M Series . . . 100 MHz Min
f
max
(internal feedback)
TIBPAL20R’ -5C Series . . . 125 MHz Min
TIBPAL20R’ -7M Series . . . 100 MHz Min
f
max
(external feedback)
TIBPAL20R’ -5C Series . . . 117 MHz Min
TIBPAL20R’ -7M Series . . . 74 MHz Min
Propagation Delay
TIBPAL20L8-5C Series . . . 5 ns Max
TIBPAL20L8-7M Series . . . 7 ns Max
TIBPAL20R’ -5C Series
(CLK-to-Q) . . . 4 ns Max
TIBPAL20R’ -7M Series
(CLK-to-Q) . . . 6.5 ns Max
Functionally Equivalent, but Faster Than,
Existing 24-Pin PLDs
Preload Capability on Output Registers
Simplifies Testing
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Security Fuse Prevents Duplication
DEVICE
PAL20L8
PAL20R4
PAL20R6
PAL20R8
I
INPUTS
14
12
12
12
3-STATE
O OUTPUTS
2
0
0
0
REGISTERED
Q OUTPUTS
0
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
I/O
PORT
S
6
4
2
0
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TIBPAL20L8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
I
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
•
•
•
•
•
TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
NC
I
I
I
5
6
7
8
9
10
I
I
I
NC
V
CC
I
O
4
3 2 1 28 27 26
25
24
23
22
21
20
11
19
12 13 14 15 16 17 18
I/O
I/O
I/O
NC
I/O
I/O
I/O
description
NC
–
No internal connection
Pin assignments in operating mode
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board.
The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
This document contains information on products in more than one
phase of development. The status of each device is indicated on the
page(s) specifying its electrical characteristics.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
I
I
GND
NC
I
I
O
Copyright
©
1992, Texas Instruments Incorporated
1
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE
IMPACT-X
™
PAL
®
CIRCUITS
TIBPAL20R4’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
I/O
I/O
Q
Q
Q
Q
I/O
I/O
I
OE
TIBPAL20R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
VCC
I
I/O
I/O
Q
Q
NC
Q
Q
I/O
VCC
I
I/O
Q
Q
Q
NC
Q
Q
Q
VCC
I
Q
Q
Q
Q
NC
Q
Q
Q
OE
I
Q
OE
I
I/O
OE
I
I/O
I
I
CLK
NC
I
I
I
NC
I
I
I
I
I
I
NC
I
I
I
I
I
I
NC
I
I
I
NC
POST OFFICE BOX 655303
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I
I
GND
NC
TIBPAL20R6’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
OE
TIBPAL20R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
CLK
NC
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I
I
GND
NC
TIBPAL20R8’
C SUFFIX . . . JT OR NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I
Q
Q
Q
Q
Q
Q
Q
Q
I
OE
TIBPAL20R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
CLK
NC
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I
I
GND
NC
Pin assignments in operating mode
–
No internal connection
2
•
DALLAS, TEXAS 75265
TIBPAL20L8-5C, TIBPAL20R4-5C
TIBPAL20L8-7M, TIBPAL20R4-7M
HIGH-PERFORMANCE
IMPACT-X
™
PAL
®
CIRCUITS
functional block diagrams (positive logic)
TIBPAL20L8’
&
40 X 64
EN
≥
1
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
7
7
O
O
I/O
I/O
I/O
I/O
I/O
I/O
20 x
I
14
20
7
7
6
20
7
7
7
7
6
TIBPAL20R4’
OE
CLK
&
40 X 64
8
8
8
20
8
4
4
20
7
7
7
7
4
4
EN
≥
1
I/O
I/O
I/O
I/O
Q
≥
1
EN 2
C1
I=0 2
1D
Q
Q
Q
20 x
I
12
denotes fused inputs
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE
IMPACT-X
™
PAL
®
CIRCUITS
functional block diagrams (positive logic)
TIBPAL20R6’
OE
CLK
&
40 X 64
8
8
8
20
8
6
8
2
20
8
EN
≥
1
Q
Q
Q
≥
1
EN 2
C1
I=0 2
1D
Q
Q
Q
20 x
I
12
7
7
2
6
I/O
I/O
TIBPAL20R8’
OE
CLK
&
40 X 64
8
8
8
20
8
8
8
20
8
8
8
Q
Q
Q
Q
Q
≥
1
EN 2
C1
I=0 2
1D
Q
Q
Q
20 x
I
12
8
denotes fused inputs
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TIBPAL20L8-5C
TIBPAL20L8-7M
HIGH-PERFORMANCE
IMPACT-X
™
PAL
®
CIRCUITS
logic diagram (positive logic)
I
1
Increment
0
I
2
First Fuse
Numbers
0
40
80
120
160
200
240
280
320
360
400
440
480
520
560
600
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
2520
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
4
8
12
16
20
24
28
32
36
39
23
I
22
O
I
3
21
I/O
I
4
20
I/O
I
5
19
I/O
I
6
18
I/O
I
7
17
I/O
I
8
16
I/O
I
9
15
O
I
I
10
11
14
13
I
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

TIBPAL20R8-5CJT Related Products

TIBPAL20R8-5CJT TIBPAL20R4-7MFK TIBPAL20R4-7MJT TIBPAL20R6-5CJT TIBPAL20R4-5CJT TIBPAL20L8-5CJT
Description OT PLD, 7ns, TTL, CDIP24, CERAMIC, DIP-24 OT PLD, 10ns, TTL, CQCC28, CERAMIC, LCC-28 OT PLD, 10ns, TTL, CDIP24, CERAMIC, DIP-24 OT PLD, 7ns, TTL, CDIP24, CERAMIC, DIP-24 OT PLD, 7ns, TTL, CDIP24, CERAMIC, DIP-24 OT PLD, 7ns, TTL, CDIP24, CERAMIC, DIP-24
Maker Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics
package instruction DIP, QCCN, DIP, DIP, DIP, CERAMIC, DIP-24
Reach Compliance Code unknown unknown unknown unknown unknown unknown
JESD-30 code R-GDIP-T24 S-CQCC-N28 R-GDIP-T24 R-GDIP-T24 R-GDIP-T24 R-GDIP-T24
JESD-609 code e0 e0 e0 e0 e0 e0
Dedicated input times 12 12 12 12 12 14
Number of I/O lines - 4 4 2 4 6
Number of terminals 24 28 24 24 24 24
Maximum operating temperature 75 °C 125 °C 125 °C 75 °C 75 °C 75 °C
organize 12 DEDICATED INPUTS, 0 I/O 12 DEDICATED INPUTS, 4 I/O 12 DEDICATED INPUTS, 4 I/O 12 DEDICATED INPUTS, 2 I/O 12 DEDICATED INPUTS, 4 I/O 14 DEDICATED INPUTS, 6 I/O
Output function REGISTERED MIXED MIXED MIXED MIXED COMBINATORIAL
Package body material CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED
encapsulated code DIP QCCN DIP DIP DIP DIP
Package shape RECTANGULAR SQUARE RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE CHIP CARRIER IN-LINE IN-LINE IN-LINE IN-LINE
Programmable logic type OT PLD OT PLD OT PLD OT PLD OT PLD OT PLD
propagation delay 7 ns 10 ns 10 ns 7 ns 7 ns 7 ns
Maximum supply voltage 5.25 V 5.5 V 5.5 V 5.25 V 5.25 V 5.25 V
Minimum supply voltage 4.75 V 4.5 V 4.5 V 4.75 V 4.75 V 4.75 V
Nominal supply voltage 5 V 5 V 5 V 5 V 5 V 5 V
surface mount NO YES NO NO NO NO
technology TTL TTL TTL TTL TTL TTL
Temperature level COMMERCIAL EXTENDED MILITARY MILITARY COMMERCIAL EXTENDED COMMERCIAL EXTENDED COMMERCIAL EXTENDED
Terminal surface TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD
Terminal form THROUGH-HOLE NO LEAD THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal location DUAL QUAD DUAL DUAL DUAL DUAL
Other features REGISTER PRELOAD; POWER-UP RESET REGISTER PRELOAD; POWER-UP RESET REGISTER PRELOAD; POWER-UP RESET REGISTER PRELOAD; POWER-UP RESET REGISTER PRELOAD; POWER-UP RESET -
maximum clock frequency 111 MHz 74 MHz 74 MHz 111 MHz 111 MHz -

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