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IS61NLF25636A-7.5TQLI

Description
ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
Categorystorage    storage   
File Size524KB,37 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Environmental Compliance  
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IS61NLF25636A-7.5TQLI Overview

ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100

IS61NLF25636A-7.5TQLI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeQFP
package instructionLQFP, QFP100,.63X.87
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Factory Lead Time10 weeks
Maximum access time7.5 ns
Other featuresFLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)117 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee3
length20 mm
memory density9437184 bit
Memory IC TypeZBT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.05 A
Minimum standby current3.14 V
Maximum slew rate0.28 mA
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width14 mm
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A 
256K x 36 and 512K x 18
9Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
AUGUST 2011
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address,
data and control
DESCRIPTION
The 9 Meg 'NLF/NVF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by
18 bits, fabricated with
ISSI
's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
• Power supply:
NVF: V
dd
2.5V (± 5%), V
ddq
2.5V (± 5%)
NLF: V
dd
3.3V (± 5%), V
ddq
3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Symbol 
t
kq
t
kc
Parameter 
Clock Access Time
Cycle Time
Frequency
6.5 
6.5
7.5
133
7.5 
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev.  F
08/11/2011
1

IS61NLF25636A-7.5TQLI Related Products

IS61NLF25636A-7.5TQLI IS61NLF51218A-7.5TQLI IS61NLF51218A-7.5B3I
Description ZBT SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100 ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100 ZBT SRAM, 512KX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165
Is it lead-free? Lead free Lead free Contains lead
Is it Rohs certified? conform to conform to incompatible
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
Parts packaging code QFP QFP BGA
package instruction LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 TBGA, BGA165,11X15,40
Contacts 100 100 165
Reach Compliance Code compliant compliant compliant
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Factory Lead Time 10 weeks 10 weeks 10 weeks
Maximum access time 7.5 ns 7.5 ns 7.5 ns
Other features FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK) 117 MHz 117 MHz 117 MHz
I/O type COMMON COMMON COMMON
JESD-30 code R-PQFP-G100 R-PQFP-G100 R-PBGA-B165
JESD-609 code e3 e3 e0
length 20 mm 20 mm 15 mm
memory density 9437184 bit 9437184 bit 9437184 bit
Memory IC Type ZBT SRAM ZBT SRAM ZBT SRAM
memory width 36 18 18
Number of functions 1 1 1
Number of terminals 100 100 165
word count 262144 words 524288 words 524288 words
character code 256000 512000 512000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
organize 256KX36 512KX18 512KX18
Output characteristics 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP TBGA
Encapsulate equivalent code QFP100,.63X.87 QFP100,.63X.87 BGA165,11X15,40
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE GRID ARRAY, THIN PROFILE
Parallel/Serial PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 260 260 NOT SPECIFIED
power supply 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.6 mm 1.6 mm 1.2 mm
Maximum standby current 0.05 A 0.05 A 0.05 A
Minimum standby current 3.14 V 3.14 V 3.14 V
Maximum slew rate 0.28 mA 0.28 mA 0.28 mA
Maximum supply voltage (Vsup) 3.465 V 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING BALL
Terminal pitch 0.65 mm 0.65 mm 1 mm
Terminal location QUAD QUAD BOTTOM
Maximum time at peak reflow temperature 40 40 NOT SPECIFIED
width 14 mm 14 mm 13 mm
Humidity sensitivity level 3 3 -
Base Number Matches - 1 1
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