EE PLD, 7.5ns, 512-Cell, CMOS, PBGA352,
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | Vantis Corporation |
Reach Compliance Code | unknown |
Other features | YES |
maximum clock frequency | 100 MHz |
In-system programmable | YES |
JESD-30 code | S-PBGA-B352 |
JESD-609 code | e0 |
JTAG BST | YES |
Number of I/O lines | 256 |
Number of macro cells | 512 |
Number of terminals | 352 |
Maximum operating temperature | 70 °C |
Minimum operating temperature | |
organize | 256 I/O |
Output function | MACROCELL |
Package body material | PLASTIC/EPOXY |
encapsulated code | BGA |
Encapsulate equivalent code | BGA352,26X26,50 |
Package shape | SQUARE |
Package form | GRID ARRAY |
Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
power supply | 3.3 V |
Programmable logic type | EE PLD |
propagation delay | 7.5 ns |
Certification status | Not Qualified |
Maximum supply voltage | 3.6 V |
Minimum supply voltage | 3 V |
Nominal supply voltage | 3.3 V |
surface mount | YES |
technology | CMOS |
Temperature level | COMMERCIAL |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | BALL |
Terminal pitch | 1.27 mm |
Terminal location | BOTTOM |
Maximum time at peak reflow temperature | NOT SPECIFIED |