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Datasheet> All Categories > Analog mixed-signal IC> converter> AD2S90AP
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AD2S90AP

Description
SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC20, PLASTIC, LCC-20
CategoryAnalog mixed-signal IC    converter   
File Size850KB，13 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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AD2S90AP Overview

SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC20, PLASTIC, LCC-20

AD2S90AP Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerRochester Electronics
Parts packaging codeQLCC
package instructionQCCJ,
Contacts20
Reach Compliance Codeunknown
Maximum analog input voltage2.2 V
Maximum angular accuracy8 arc min
Converter typeSYNCHRO OR RESOLVER TO DIGITAL CONVERTER
JESD-30 codeS-PQCC-J20
JESD-609 codee0
length8.9662 mm
Humidity sensitivity level1
Maximum negative supply voltage-5.25 V
Minimum negative supply voltage-4.75 V
Nominal negative supply voltage-5 V
Number of digits12
Number of functions1
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)225
Certification statusCOMMERCIAL
Maximum seat height4.57 mm
Signal/output frequency20000 Hz
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Maximum tracking rate500 rps
width8.9662 mm

AD2S90AP Preview

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FEATURES
Complete Monolithic Resolver-to-Digital Converter
Incremental Encoder Emulation (1024-Line)
Absolute Serial Data (12-Bit)
Differential Inputs
12-Bit Resolution
Industrial Temperature Range
20-Lead PLCC
Low Power (50 mW)
APPLICATIONS
Industrial Motor Control
Servo Motor Control
Industrial Gauging
Encoder Emulation
Automotive Motion Sensing and Control
Factory Automation
Limit Switching
Low Cost, Complete 12-Bit
Resolver-to-Digital Converter
AD2S90
FUNCTIONAL BLOCK DIAGRAM
REF
SIN
SIN LO
COS
COS LO
NMC
A
B
NM
CS
HIGH ACCURACY
ANGLE
SIN COS
MULTIPLIER
DIGITAL
ANGLE
DECODE
LOGIC
UP-DOWN
COUNTER
SIN ( –
)
P.S.D. AND VEL
FREQUENCY
SHAPING
CLKOUT
HIGH
DYNAMIC
RANGE V.C.O.
ERROR
AMPLIFIER
U/D
CLK
DIR
LATCH
SCLK
DATA
SERIAL INTERFACE
GENERAL DESCRIPTION
The AD2S90 is a complete 12-bit resolution tracking resolver-
to-digital converter. No external components are required to
operate the device.
The converter accepts 2 V rms
±
10% input signals in the range
3 kHz–20 kHz on the SIN, COS and REF inputs. A Type II
servo loop is employed to track the inputs and convert the input
SIN and COS information into a digital representation of the
input angle. The bandwidth of the converter is set internally at
1 kHz within the tolerances of the device. The guaranteed maxi-
mum tracking rate is 500 rps.
Angular position output information is available in two forms,
absolute serial binary and incremental A quad B.
The absolute serial binary output is 12-bit (1 in 4096). The data
output pin is high impedance when Chip Select
CS
is logic HI.
This allows the connection of multiple converters onto a com-
mon bus. Absolute angular information in serial pure binary
form is accessed by
CS
followed by the application of an exter-
nal clock (SCLK) with a maximum rate of 2 MHz.
The encoder emulation outputs A, B and NM continuously
produce signals equivalent to a 1024 line encoder. When de-
coded this corresponds to 12 bits of resolution. Three common
north marker pulsewidths are selected via a single pin (NMC).
An analog velocity output signal provides a representation of
velocity from a rotating resolver shaft traveling in either a clock-
wise or counterclockwise direction.
The AD2S90 operates on
±
5 V dc
±
5% power supplies and is
fabricated on Analog Devices’ Linear Compatible CMOS pro-
cess (LC
2
MOS). LC
2
MOS is a mixed technology process that
combines precision bipolar circuits with low power CMOS logic
circuits.
PRODUCT HIGHLIGHTS
Complete Resolver-Digital Interface.
The AD2S90 provides
the complete solution for digitizing resolver signals (12-bit reso-
lution) without the need for external components.
Dual Format Position Data.
Incremental encoder emulation
in standard A QUAD B format with selectable North Marker
width. Absolute serial 12-bit angular binary position data
accessed via simple 3-wire interface.
Single High Accuracy Grade in Low Cost Package.
±10.6
arc
minutes of angular accuracy available in a 20-lead PLCC.
Low Power.
Typically 50 mW power consumption.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD2S90–SPECIFICATIONS
Parameter
SIGNAL INPUTS
Voltage Amplitude
Frequency
Input Bias Current
Input Impedance
Common-Mode Volts
1
CMRR
REFERENCE INPUT
Voltage Amplitude
Frequency
Input Bias Current
Input Impedance
Permissible Phase Shift
CONVERTER DYNAMICS
Bandwidth
Maximum Tracking Rate
Maximum VCO Rate (CLKOUT)
Settling Time
1° Step
179° Step
ACCURACY
Angular Accuracy
2
Repeatability
3
VELOCITY OUTPUT
Scaling
Output Voltage at 500 rps
Load Drive Capability
LOGIC INPUTS SCLK,
CS
Input High Voltage (V
INH
)
Input Low Voltage (V
INL
)
Input Current (I
IN
)
Input Capacitance
LOGIC OUTPUTS DATA, A, B,
4
NM, CLKOUT, DIR
Output High Voltage
Output Low Voltage
SERIAL CLOCK (SCLK)
SCLK Input Rate
NORTH MARKER CONTROL (NMC)
90°
180°
360°
POWER SUPPLIES
V
DD
V
SS
I
DD
I
SS
+4.75
–0.75
–4.75
+4.75
–4.75
120
±
2.78
Min
1.8
3
1.0
(V
DD
= +5 V 5%, V
SS
= –5 V
otherwise noted)
Typ
2.0
Max
2.2
20
100
100
5%, AGND = DGND = 0 V, T
A
= –40 C to +85 C unless
Units
V rms
kHz
nA
MΩ
mV peak
dB
V rms
kHz
nA
kΩ
Degrees
Hz
rps
MHz
ms
ms
arc min
LSB
rps/V dc
V dc
µA
V dc
V dc
µA
pF
Test Condition
Sinusoidal Waveforms, Differential
SIN to SINLO, COS to COSLO
V
IN
= 2
±
10% V rms
V
IN
= 2
±
10% V rms
CMV @ SINLO, COSLO w.r.t.
AGND @ 10 kHz
Sinusoidal Waveform
60
1.8
3
100
–10
700
500
2.048
840
2.0
3.35
20
100
+10
1000
Relative to SIN, COS Inputs
2
7
20
±
10.6 + 1 LSB
1
150
±
3.33
180
±
4.17
±
250
V
OUT
=
±2.5
V dc (typ), R
L
≥
10 kΩ
V
DD
= +5 V dc, V
SS
= –5 V dc
V
DD
= +5 V dc, V
SS
= –5 V dc
3.5
1.5
10
10
4.0
1.0
0.4
2
+5.0
DGND
–5.0
+5.00
–5.00
+5.25
+0.75
–5.25
+5.25
–5.25
10
10
V dc
V dc
V dc
MHz
V dc
V dc
V dc
V dc
V dc
mA
mA
V
DD
= +5 V dc, V
SS
= –5 V dc
I
OH
= 1 mA
I
OL
= 1 mA
I
OL
= 400
µA
North Marker Width Relative to
“A” Cycle
NOTES
1
If the tolerance on signal inputs =
±
5%, then CMV = 200 mV.
2
1 LSB = 5.3 arc minute.
3
Specified at constant temperature.
4
Output load drive capability.
Specifications subject to change without notice.
–2–
REV. D
AD2S90
TIMING CHARACTERISTICS
CSB
1, 2
(V
DD
= +5 V
t
2
5%, V
SS
= –5 V
otherwise noted)
5%, AGND = DGND = 0 V, T
A
= –40 C to +85 C unless
t
6
t
3
SCLK
t
4
DATA
MSB
LSB
t*
t
1
t
5
t
7
*
THE MINIMUM ACCESS TIME: USER DEPENDENT
Figure 1. Serial Interface
NOTES
1
Timing data are not 100% production tested. Sample tested at +25°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using
10 pF, 100 kΩ load.
2
Capacitance of data pin in high impedance state = 15 pF.
Parameter
t
1
t
2 1
t
3
t
4
t
5
t
6
t
7
AD2S90
150
600
250
250
100
600
150
Units
ns max
ns min
ns min
ns min
ns max
ns min
ns max
Test Conditions/Notes
CS
to DATA Enable
CS
to 1st SCLK Negative Edge
SCLK Low Pulse
SCLK High Pulse
SCLK Negative Edge to DATA Valid
CS
High Pulsewidth
CS
High to DATA High Z (Bus Relinquish)
NOTE
1
SCLK can only be applied after t
2
has elapsed.
A
COUNTER IS CLOCKED
ON THIS EDGE
B
CLKOUT
t
CLK
t
ABN
90
A, B, NM
NM
180
t
DIR
DIR
360
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
Figure 2. Incremental Encoder
Figure 3. DIR/CLKOUT/A, B and NM Timing
AD2S90
Parameter
t
DIR
t
CLK
t
ABN
Min
250
Max
200
400
250
Units
ns
ns
ns
Test Conditions/Notes
DIR to CLKOUT Positive Edge
CLKOUT Pulsewidth
CLKOUT Negative Edge to A, B and NM Transition
REV. D
–3–
AD2S90
Power Supply Voltage (V
DD
– V
SS
) . . . . . . . . . .
±
5 V dc
±
5%
Analog Input Voltage (SIN, COS & REF) . . . . . 2 V rms
±
10%
Signal and Reference Harmonic Distortion . . . . . . . . . . . . 10%
Phase Shift between Signal and Reference . . . . . . . . . . . . .
±
10°
Ambient Operating Temperature Range
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED OPERATING CONDITIONS
PIN DESCRIPTIONS
Pin
No. Mnemonic Function
1
2
AGND
SIN
Analog ground, reference ground.
SIN channel noninverting input connect to
resolver SIN HI output. SIN to SIN LO =
2 V rms
±
10%.
SIN channel inverting input connect to
resolver SIN LO.
Serial interface data output. High impedance
with
CS
= HI. Enabled by
CS
= 0.
Serial interface clock. Data is clocked out on
“first” negative edge of SCLK after a LO transi-
tion on
CS.
12 SCLK pulses to clock data out.
Chip select. Active LO. Logic LO transition
enables DATA output.
Encoder A output.
Encoder B output.
Encoder North Marker emulation output.
Pulse triggered as code passes through zero.
Three common pulsewidths available.
Indicates direction of rotation of input.
Logic HI = increasing angular rotation.
Logic LO = decreasing angular rotation.
Digital power ground return.
Negative power supply, –5 V dc
±
5%.
Positive power supply, +5 V dc
±
5%.
Positive power supply, +5 V dc
±
5%. Must
be connected to Pin 13.
North marker width control. Internally pulled
HI via 50 kΩ nominal.
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V dc to +7.0 V dc
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . +0.3 V dc to –7.0 V dc
AGND to DGND . . . . . . . . . . . . –0.3 V dc to V
DD
+ 0.3 V dc
Analog Inputs to AGND
REF . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V dc to V
DD
+ 0.3 V dc
SIN, SIN LO . . . . . . . . . . . V
SS
– 0.3 V dc to V
DD
+ 0.3 V dc
COS, COS LO . . . . . . . . . . V
SS
– 0.3 V dc to V
DD
+ 0.3 V dc
Analog Output to AGND
VEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
Digital Inputs to DGND, CSB,
SCLK, RES . . . . . . . . . . . . . . . –0.3 V dc to V
DD
+ 0.3 V dc
Digital Outputs to DGND, NM, A, B,
DIR, CLKOUT DATA . . . . . . –0.3 V dc to V
DD
+ 0.3 V dc
Operating Temperature Range
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . . . 300 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
3
4
5
SIN LO
DATA
SCLK
6
7
8
9
CS
A
B
NM
10
DIR
11
12
13
14
DGND
V
SS
V
DD
V
DD
NMC
ORDERING GUIDE
Model
Temperature Range Accuracy
Package Option
15
16
AD2S90AP –40°C to +85°C
10.6 arc min P-20A
PIN CONFIGURATION
COS LO
SIN LO
AGND
CLKOUT Internal VCO clock output. Indicates angular
velocity of input signals. Max nominal rate =
1.536 MHz. CLKOUT is a 300 ns positive pulse.
VEL
Indicates angular velocity of input signals.
Positive voltage w.r.t. AGND indicates in-
creasing angle. FSD = 375 rps.
Converter reference input. Normally derived
from resolver primary excitation. REF = 2 V
rms nominal. Phase shift w.r.t. COS and SIN
=
±
10° max
COS channel inverting input. Connect to
resolver COS LO.
COS channel noninverting input. Connect to
resolver COS HI output. COS = 2 V rms
±
10%.
17
3
2
1
COS
20
SIN
19
DATA
4
SCLK
5
CS
6
PIN 1
18
IDENTIFIER
17
REF
VEL
CLKOUT
NMC
V
DD
18
REF
AD2S90
TOP VIEW
(Not to Scale)
16
15
14
A
7
B
8
9
19
20
COS LO
COS
10
11
12
13
CAUTION
The AD2S90 features an input protection circuit consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charges Device Model).
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. For further information on ESD precautions, refer to Analog Devices
ESD
Prevention Manual.
DGND
V
DD
V
SS
NM
DIR
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. D
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  5. I hope the program about the sequential queue in the data structure will be helpful to everyone.
  6. Drop test national standard
  7. Simple SMS code
  8. Optimal minimum switching loss SVPWM floor water heating variable frequency speed regulation system
  9. Temperature Control DC Motor Speed_Keil C
  10. \"Simulation Technology Lecture Notes (Volume 1)\" Huawei

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