Datasheet
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Radiation Hardened CMOS Dual SPDT Analog Switch
The
HS-303ARH, HS-303AEH, HS-303BRH,
HS-303BEH
analog switches are monolithic devices
fabricated using the Renesas dielectrically isolated
Radiation Hardened Silicon Gate (RSG) process
technology to ensure latch-up free operation. They
are pinout compatible and functionally equivalent to
the HS-303RH, but offer improved 300kRAD(Si) total
dose capability. These switches offer low-resistance
switching performance for analog voltages up to the
supply rails. ON-resistance is low and stays
reasonably constant over the full range of operating
voltage and current. ON-resistance also stays
reasonably constant when exposed to radiation.
Break-before-make switching is controlled by 5V
digital inputs. The HS-303ARH and HS-303AEH
should be operated with nominal ±15V supplies, while
the HS-303BRH and HS-303BEH should be operated
with nominal ±12V supplies.
Features
• QML, per MIL-PRF-38535
• Radiation performance
○ Total dose: 3x10
5
rad(Si)
○ SEE: For LET = 60MeV•cm
2
/mg at 60° incident
angle, <150pC charge transferred to the output of
an off switch (based on SOI design calculations)
• No latch-up, dielectrically isolated device islands
• Pinout and functionally compatible with Renesas
HS-303RH and HI-303 series analog switches
• Analog signal range equal to the supply voltage
range
• Low leakage: 100nA (max, post-rad)
• Low r
ON
: 70Ω (max, post-rad)
• Low standby supply current: +150µA/-100µA
(max, post-rad)
Specifications
Specifications for Rad Hard QML devices are
controlled by the Defense Logistics Agency Land and
Maritime (DLA). The SMD number listed in the
following must be used when ordering.
Detailed Electrical Specifications for the HS-303ARH,
HS-303AEH, HS-303BRH, HS-303BEH are contained
in SMD
5962-95813.
Pin Configurations
HS1-303ARH, HS-303BRH
(SBDIP), CDIP2-T14
Top View
NC
S3
D3
D1
S1
IN1
1
2
3
4
5
6
7
14 V+
13 S4
12 D4
11 D2
10 S2
9 IN2
8 V-
Functional Diagram
IN
N
P
D
GND
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
(FLATPACK) CDFP3-F14
Top View
Truth Table
Logic
0
1
SW1 and SW2
OFF
ON
SW3 and SW4
ON
OFF
NC
S3
D3
D1
S1
IN1
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
S4
D4
D2
S2
IN2
V-
FN6411 Rev.4.00
Jul.18.19
Page 1 of 7
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
1. Overview
1.
1.1
Overview
Ordering Information
Ordering Number
(Note
2)
Part Number
(Note
1)
HS1-303ARH-8
HS9-303ARH-8
HS0-303ARH-Q
HS0-303AEH-Q
HS1-303ARH-Q
HS1-303AEH-Q
HS9-303ARH-Q
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
HS9-303AEH-Q
HS1-303BRH-8
HS9-303BRH-8
HS0-303BRH-Q
HS0-303BEH-Q
HS1-303BRH-Q
HS1-303BEH-Q
HS9-303BRH-Q
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
HS9-303BEH-Q
Temp. Range
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Package
(RoHS Compliant)
14 LD SBDIP
14 LD Flatpack
Die
Die
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
Die
14 LD SBDIP
14 LD Flatpack
14 LD Flatpack
14 LD SBDIP
14 LD Flatpack
Die
Die
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
Die
14 LD SBDIP
14 LD Flatpack
14 LD Flatpack
D14.3
K14.A
K14.A
D14.3
D14.3
K14.A
D14.3
K14.A
K14.A
D14.3
K14.A
D14.3
D14.3
K14.A
Pkg.
Dwg. #
D14.3
K14.A
5962F9581304QCC
5962F9581304QXC
5962F9581304V9A
5962F9581306V9A
5962F9581304VCC
5962F9581306VCC
5962F9581304VXC
N/A
N/A
N/A
5962F9581306VXC
5962F9581305QCC
5962F9581305QXC
5962F9581305V9A
5962F9581307V9A
5962F9581305VCC
5962F9581307VCC
5962F9581305VXC
N/A
N/A
N/A
5962F9581307VXC
Notes:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers
listed must be used when ordering.
FN6411 Rev.4.00
Jul.18.19
Page 2 of 7
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
2. Die Characteristics
2.
Die Characteristics
Die and Assembly Related Information
2690µm x 5200µm (106mils x 205mils)
Thickness: 483µm ± 25.4µm (19mils ± 1mil)
Table 1.
Dimensions
Die Information
Interface Materials
Glassivation
Top Metallization
Substrate
Backside Finish
Assembly Information
Substrate Potential
Additional Information
Worst Case Current Density
Transistor Count
Weight of Packaged Device
Lid Characteristics
<2.0 x 10
5
A/cm
2
332
0.31 grams
Finish: Gold
Potential: Grounded, tied to package pin 2
Unbiased (DI)
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0k
Å
± 1.0k
Å
Type: AlSiCu
Thickness: 16.0k
Å
± 2k
Å
Radiation Hardened Silicon Gate,
Dielectric Isolation
Silicon
2.1
Metallization Mask Layout
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
IN2
V-
V+
GND
IN1
D4
D2
S4
S2
S1
S3
FN6411 Rev.4.00
Jul.18.19
D3
D1
Page 3 of 7
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
3. Revision History
3.
Rev.
4.00
Revision History
Date
Jul.18.19
Description
Applied new formatting throughout.
Updated links throughout.
Updated second Features bullet.
Updated ordering information table removed package drawing for die related parts and updated notes.
Added Revision History section.
Updated Disclaimer.
FN6411 Rev.4.00
Jul.18.19
Page 4 of 7
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
4. Package Outline Drawings
For the most recent package outline drawing, see
D14.3.
4.
Package Outline Drawings
c1
-A-
-D-
BASE
METAL
M
-B-
bbb S
C A-B S
D
S2
-C-
Q
A
L
A A
b
D S
b1
M
(b)
SECTION A-A
(c)
LEAD FINISH
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, Configuration C)
14 Lead Ceramic Dual In-Line Metal Seal Package (SBDIP)
INCHES
SYMBOL
A
b
b1
b2
b3
c
c1
D
E
e
eA
eA/2
L
Q
S1
S2
a
aaa
bbb
ccc
M
N
MIN
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.220
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MILLIMETERS
MIN
-
0.36
0.36
1.14
0.58
0.20
0.20
-
5.59
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
2.54 BSC
7.62 BSC
3.81 BSC
3.18
0.38
0.13
0.13
90
o
-
-
-
-
14
5.08
1.52
-
-
105
o
0.38
0.76
0.25
0.038
NOTES
-
2
3
-
4
2
3
-
-
-
-
-
-
5
6
7
-
-
-
-
2
8
Rev. 0 4/94
E
BASE
PLANE
SEATING
PLANE
S1
b2
e
A
e
e
A/2
c
0.100 BSC
0.300 BSC
0.150 BSC
0.125
0.015
0.005
0.005
90
o
-
-
-
-
14
0.200
0.060
-
-
105
o
0.015
0.030
0.010
0.0015
ccc M C A - B S D S
aaa
M C A - B S D S
Notes:
1. Index area: A notch or a pin one identification mark shall be
located adjacent to pin one and shall be located within the
shaded area shown. The manufacturer’s identification shall not
be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
FN6411 Rev.4.00
Jul.18.19
Page 5 of 7
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