M58LW064A
M58LW064B
64 Mbit (4Mb x16 or 2Mb x32, Uniform Block)
3V Supply Flash Memories
PRELIMINARY DATA
s
WIDE x16/x32 DATA BUS for HIGH
BANDWIDTH
– M58LW064A x16 DATA BITS
– M58LW064B x16/x32 DATA BITS
86
s
SUPPLY VOLTAGE
– V
CC
= 2.7V to 3.6V Supply Voltage
– V
CCQ
= 1.8V to 3.6V Input/Output Supply
Voltage
TSOP56 (N)
14 x 20 mm
1
TSOP86 Type II (NC)
s
SYNCHRONOUS/ASYNCHRONOUS READ
– Synchronous Burst read
– Asynchronous Random Read
– Address Latch Configurable
– Page Read
PQFP80 (T)
LBGA54 (ZA)
8 x 8 solder balls
BGA
s
PIPELINED SYNCHRONOUS BURST
INTERFACE
ACCESS TIME
– Synchronous Burst Read up to 66MHz
– Asynchronous Page Mode Read 150/25ns
– Random Read 150ns
VCC VCCQ
22
A1-A22
VPP
W
E
G
RP
L
B
K
WORD
(1)
s
Figure 1. Logic Diagram
s
PROGRAMMING TIME
– 16 Word or 8 Double-Word Write Buffer
– 12µs Word effective programming time
16
DQ0-DQ15
16
DQ16-DQ31
(1)
s
s
64 UNIFORM 64 KWord MEMORY BLOCKS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code M58LW064A: 17h
– Device Code M58LW064B: 14h
RB
M58LW064A
M58LW064B
R
VSS
AI03223
Note: 1. M58LW064B only.
July 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M58LW064A, M58LW064B
Table 1. Signal Names
A1-A22
A2-A22
Address Inputs x16 Organization
Address inputs x32 Organization
Data Input/Output x16 and x32
Organization Command Input,
Electronic Signature Output, Block
Protection Status Output, Status
Register Output
Data Input/Output x16 and x32
Organization
Data Input/Output x32 Organization
Burst Address Advance
Chip Enable
Output Enable
Burst Clock
Latch Enable
Valid Data Ready (open drain output)
Ready/Busy (open drain output)
Reset/Power-down
Program/Erase Enable
Write Enable
Word Organization (M58LW064B only)
Supply Voltage
Input/Output Supply Voltage
Ground
Not Connected Internally
DQ0-DQ7
DQ8-DQ15
DQ16-DQ31
B
E
G
K
L
R
RB
RP
V
PP
W
WORD
V
CC
V
CCQ
V
SS
NC
DESCRIPTION
The M58LW064 is a non-volatile Flash memory
that may be erased electrically at the block level
and programmed in-system on a 16 Word or 8
Double-Word basis using a 2.7V to 3.6V supply for
the core and a supply down to 1.8V for the Input
and Output buffers. The M58LW064A is organized
as 4Mb x16. The M58LW064B is organized as
4Mb x16 or 2Mb x32 bit organization selectable by
the Word Organization input, WORD. Both memo-
ries are internally configured as 64 blocks of 1 Mbit
each. The memories support Asynchronous Ran-
dom and Latch Enable Controlled Read with Page
mode as well as Synchronous Burst Read with a
configurable burst. They also support pipelined
synchronous Burst Read. Writing is Asynchronous
or Asynchronous Latch Enable Controlled.
The configurable synchronous burst read interface
allows a high data transfer rate controlled by the
Burst Clock signal, K. The interface is capable of
bursting fixed or unlimited lengths of data. The
burst type, latency and length are configurable and
can be easily adapted to a large variety of system
clock frequencies and microprocessors. A 16
Word or 8 Double-Word Write Buffer improves ef-
fective programming speed by up to 20 times
when data is programmed in full buffer increments.
Effective Word programming takes typically 12µs.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. Program and Erase operations can
be suspended in order to perform Read operations
in any other block and then resumed; suspended
Erase operations also allow Program operations
to be performed in other blocks. All blocks are pro-
tected against spurious programming and erase
cycles at power-up. Any block can be separately
protected at any time. The block protection bits
can also be reset, this is executed as one se-
quence for all blocks simultaneously. Block protec-
tion can be temporarily disabled. Each block can
be programmed and erased over 100,000 times.
Block erase is performed in typically 1 second.
An internal Command Interface (C.I.) decodes In-
structions to access/modify the memory content.
The Program/Erase Controller (P/E.C.) automati-
cally executes the algorithms taking care of the
timings required by the program and erase opera-
tions. Verification is internally performed and a
Status Register tracks the status of the operations.
The Ready/Busy output, RB, indicates the com-
pletion of operations.
Instructions are written to the memory through the
Command Interface (C.I.) using standard micro-
processor write timings. The memory supports the
Common Flash Interface (CFI) command set defi-
nition.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consump-
tion is lower than in the normal standby mode, the
memory is write protected and both the Status and
the Burst Configuration Registers are cleared. A
recovery time is required when the RP input goes
High.
The memory is offered in various packages. The
M58LW064A is available in TSOP56 (14 x 20 mm)
and LBGA54 1 mm ball pitch. The M58LW064B is
available in PQFP80 and TSOP56 Type II.
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