BUK9Y14-40B
N-channel TrenchMOS logic level FET
Rev. 03 — 2 June 2008
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using NXP High Performance Automotive (HPA) TrenchMOS technology. This
product has been designed and qualified to the appropriate AEC standard for use in
automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Q101 compliant
Suitable for thermally demanding
environments due to 175
°C
rating
1.3 Applications
Air bag
Automotive transmission control
Fuel pump and injection
Automotive ABS systems
Diesel injection systems
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Q
GD
Quick reference
Parameter
drain-source voltage
drain current
total power dissipation
gate-drain charge
Conditions
T
j
≥
25
°C;
T
j
≤
175
°C
V
GS
= 5 V; T
mb
= 25
°C;
see
Figure 4
and
1
T
mb
= 25
°C;
see
Figure 2
V
GS
= 5 V; I
D
= 10 A;
V
DS
= 32 V; see
Figure 14
V
GS
= 5 V; I
D
= 20 A;
T
j
= 25
°C;
see
Figure 12
and
13
I
D
= 56 A; V
sup
≤
40 V;
R
GS
= 50
Ω;
V
GS
= 5 V;
T
j(init)
= 25
°C;
unclamped
Min
-
-
-
-
Typ
-
-
-
9
Max
40
56
85
-
Unit
V
A
W
nC
Dynamic characteristics
Static characteristics
R
DSon
drain-source on-state
resistance
-
12
14
mΩ
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source
avalanche energy
-
-
89
mJ
NXP Semiconductors
BUK9Y14-40B
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1, 2, 3
4
mb
Pinning
Symbol
S
G
D
Description
source
gate
mounting base;
connected to drain
1 2 3 4
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9Y14-40B
LFPAK
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
drain-source voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
I
D
= 56 A; V
sup
≤
40 V; R
GS
= 50
Ω;
V
GS
= 5 V;
T
j(init)
= 25
°C;
unclamped
see
Figure 3
[1][2]
[3]
Conditions
T
j
≥
25
°C;
T
j
≤
175
°C
T
mb
= 25
°C;
V
GS
= 5 V; see
Figure 4
and
1
T
mb
= 100
°C;
V
GS
= 5 V; see
Figure 1
T
mb
= 25
°C;
t
p
≤
10
μs;
pulsed; see
Figure 4
T
mb
= 25
°C;
see
Figure 2
Min
-
15
-
-
-
-
-55
-55
-
Max
40
15
56
40
226
85
175
175
89
Unit
V
V
A
A
A
W
°C
°C
mJ
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source avalanche
energy
E
DS(AL)R
repetitive drain-source
avalanche energy
Source-drain diode
I
S
I
SM
[1]
[2]
[3]
-
-
J
source current
peak source current
T
mb
= 25
°C
t
p
≤
10
μs;
pulsed; T
mb
= 25
°C
-
-
56
226
A
A
Single-pulse avalanche rating limited by maximum junction temperature of 175
°C.
Repetitive avalanche rating limited by average junction temperature of 170
°C.
Refer to application note AN10273 for further information.
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
2 of 12
NXP Semiconductors
BUK9Y14-40B
N-channel TrenchMOS logic level FET
60
I
D
(A)
40
003aab217
120
P
der
(%)
80
03na19
20
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
P
tot
P
tot
(25°C )
200
V
GS
5V
P
der
=
× 100 %
Fig 1. Continuous drain current as a function of
mounting base temperature
10
2
I
AL
(A)
10
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aab220
(1)
(2)
(3)
1
10
-1
10
-3
10
-2
10
-1
1 t (ms) 10
AL
(1) Single pulse;T
j
= 25
°C.
(2) Single pulse;T
j
= 150
°C.
(3) Repetitive.
Fig 3. Single-shot and repetitive avalanche rating; avalanche current as a function of avalanche period
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
3 of 12
NXP Semiconductors
BUK9Y14-40B
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
003aab218
t
p
= 10
μs
100
μs
10
DC
1
1 ms
10 ms
100 ms
10
−1
1
10
V
DS
(V)
10
2
T
mb
= 25
°C; I
DM
is single pulse
Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
see
Figure 5
Min
-
Typ
-
Max
1.8
Unit
K/W
10
Z
th (j-mb)
(K/W)
1
03nm01
δ
= 0.5
0.2
0.1
10
-1
P
δ
=
0.05
0.02
t
p
t
p
T
t
T
10
-2
10
-6
single shot
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
4 of 12
NXP Semiconductors
BUK9Y14-40B
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
Conditions
I
D
= 250
μA;
V
GS
= 0 V;
T
j
= 25
°C
I
D
= 250
μA;
V
GS
= 0 V;
T
j
= -55
°C
V
GS(th)
gate-source threshold I
D
= 1 mA; V
DS
= V
GS
;
voltage
T
j
= -55
°C;
see
Figure 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25
°C;
see
Figure 11
and
10
I
D
= 1 mA; V
DS
= V
GS
;
T
j
= 175
°C;
see
Figure 10
I
DSS
drain leakage current
V
DS
= 40 V; V
GS
= 0 V;
T
j
= 175
°C
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25
°C
I
GSS
gate leakage current
V
DS
= 0 V; V
GS
= 20 V; T
j
= 25
°C
V
DS
= 0 V; V
GS
= -20 V;
T
j
= 25
°C
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 20 A; T
j
= 175
°C;
see
Figure 12
V
GS
= 4.5 V; I
D
= 20 A; T
j
= 25
°C
V
GS
= 10 V; I
D
= 20 A; T
j
= 25
°C
V
GS
= 5 V; I
D
= 20 A; T
j
= 25
°C;
see
Figure 12
and
13
Source-drain diode
V
SD
t
rr
Q
r
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
source-drain voltage
I
S
= 25 A; V
GS
= 0 V; T
j
= 25
°C;
see
Figure 16
-
-
-
-
-
-
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz; T
j
= 25
°C;
see
Figure 15
-
-
-
-
-
-
-
0.85
50
26
21
3.7
9
1360
274
147
15
34
68
42
1.2
-
-
-
-
-
1800
330
200
-
-
-
-
V
ns
nC
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
Min
40
36
-
1.1
0.5
-
-
-
-
-
-
-
-
Typ
-
-
-
1.5
-
-
0.02
2
2
-
-
9
12
Max
-
-
2.3
2
-
500
1
100
100
26
16
11
14
Unit
V
V
V
V
V
μA
μA
nA
nA
mΩ
mΩ
mΩ
mΩ
Static characteristics
reverse recovery time I
S
= 20 A; dI
S
/dt = -100 A/μs;
V
GS
= 0 V; V
DS
= 30 V
recovered charge
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
I
D
= 10 A; V
DS
= 32 V; V
GS
= 5 V;
see
Figure 14
Dynamic characteristics
V
DS
= 30 V; R
L
= 2.5
Ω;
V
GS
= 5 V; R
G(ext)
= 10
Ω
BUK9Y14-40B_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 2 June 2008
5 of 12
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