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MC74VHC157
Quad 2- Channel Multiplexer
-
The MC74VHC157 is an advanced high-
-speed CMOS quad
2-
-channel multiplexer, fabricated with silicon gate CMOS
technology. It achieves high-
-speed operation similar to equivalent
Bipolar-
-Schottky TTL, while maintaining CMOS low-
-power
dissipation.
It consists of four 2-
-input digital multiplexers with common select
(S) and enable (E) inputs. When E is held High, selection of data is
inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
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MARKING
DIAGRAMS
16
9
SOIC-
-16
D SUFFIX
CASE 751B
VHC157
AWLYYWW
1
8
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: t
PD
= 4.1 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 4
mA
(Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 82 FETs
These devices are available in Pb-
-free package(s). Specifications herein
apply to both standard and Pb-
-free devices. Please see our website at
www.onsemi.com for specific Pb-
-free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
16
9
TSSOP-
-16
DT SUFFIX
CASE 948F
VHC
157
ALYW
1
8
16
9
SOIC EIAJ-
-16
M SUFFIX
CASE 966
74VHC157
ALYW
1
8
S
A0
B0
Y0
A1
B1
Y1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
E
A3
B3
Y3
A2
B2
Y2
A
L, WL
Y, YY
W, WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74VHC157D
MC74VHC157DR2
MC74VHC157DT
Package
SOIC--16
SOIC--16
TSSOP--16
Shipping
48 Units/Rail
2500 Units/Reel
96 Units/Rail
MC74VHC157DTR2 TSSOP--16 2500 Units/Reel
MC74VHC157M
MC74VHC157MEL
SOIC
EIAJ--16
SOIC
EIAJ--16
50 Units/Rail
2000 Units/Reel
Figure 1. Pin Assignment
©
Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 5
-
1
Publication Order Number:
MC74VHC157/D
MC74VHC157
A0
B0
A1
B1
NIBBLE
INPUTS
A2
B2
A3
B3
E
S
2
3
5
6
11
10
14
13
15
1
12 Y3
9
Y2
7
Y1
DATA
OUTPUTS
4
Y0
Figure 2. Expanded Logic Diagram
E
S
A0
B0
A1
B1
15
1
2
3
5
6
EN
G1
1
1
MUX
4
7
9
12
Y0
Y1
Y2
Y3
11
A2
10
B2
14
A3
13
B3
Figure 3. IEC Logic Symbol
FUNCTION TABLE
Inputs
E
H
L
L
S
X
L
H
Outputs
Y0 - Y3
-
L
A0--A3
B0--B3
A0 -- A3, B0 -- B3 = the levels
of the respective Data--Word
Inputs.
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2
MC74VHC157
MAXIMUM RATINGS
(Note 1)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
T
STG
T
L
T
J
θ
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% -- 35%
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 85_C (Note 5)
V
I
<
GND
V
O
<
GND
Parameter
Value
−0.5
to
+7.0
−0.5
to V
CC
+7.0
−0.5
to V
CC
+7.0
−20
±20
±25
±100
−65
to
+150
260
+150
250
250
Level 1
UL--94--VO (0.125 in)
>2000
>200
N/A
±500
V
Unit
V
V
V
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
I
Latch--Up
Latch--Up Performance
mA
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum--rated
conditions is not implied.
2. Tested to EIA/JESD22--A114--A.
3. Tested to EIA/JESD22--A115--A.
4. Tested to JESD22--C101--A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range, all Package Types
Input Rise or Fall Time
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
(Note 6)
Characteristics
Min
2.0
0
0
−55
0
0
Max
5.5
5.5
V
CC
125
100
20
Unit
V
V
V
_C
ns/V
6. Unused inputs may not be left open. All inputs must be tied to a high--logic voltage level or a low--logic input voltage level.
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
_C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
T
J
= 130_C
T
J
= 120_C
T
J
= 100_C
T
J
= 110_C
T
J
= 90_C
T
J
= 80_C
100
TIME, YEARS
1
1
10
1000
Figure 4. Failure Rate vs. Time Junction Temperature
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3
MC74VHC157
DC CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
V
IL
V
OH
Parameter
High--Level
Input Voltage
Low--Level
Input Voltage
High--Level
Output Voltage
V
IN
= V
IH
or V
IL
I
OH
= --50
mA
V
IN
= V
IH
or V
IL
I
OH
= --4 mA
I
OH
= --8 mA
V
OL
Low--Level
Output Voltage
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OH
= 4 mA
I
OH
= 8 mA
I
IN
I
CC
Input Leakage
Current
Quiescent
Supply Current
V
IN
= 5.5 V or
GND
V
IN
= V
CC
or
GND
Condition
(V)
2.0
3.0 to 5.5
2.0
3.0 to 5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
0 to 5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
4.0
2.0
3.0
4.5
Min
1.5
0.7 V
CC
0.5
0.3 V
CC
1.9
2.9
4.4
2.48
3.8
0.1
0.1
0.1
0.44
0.44
±1.0
40.0
T
A
= 25_C
Typ
Max
T
A
≤85_C
Min
1.5
0.7 V
CC
0.5
0.3 V
CC
1.9
2.9
4.4
2.34
3.66
0.1
0.1
0.1
0.52
0.52
±1.0
40.0
mA
mA
V
Max
-
-55_C
≤T
A
≤125_C
Min
1.5
0.7 V
CC
0.5
0.3 V
CC
Max
Unit
V
V
V
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns)
T
A
= 25_C
Symbol
t
PLH
,
t
PHL
Characteristic
Propagation Delay,
A to B to Y
Test Conditions
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
t
PLH
,
t
PHL
Propagation Delay,
S to Y
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
t
PLH
,
t
PHL
Propagation Delay,
E to Y
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
C
IN
Input Capacitance
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
Min
Typ
6.2
8.7
4.1
5.6
8.4
10.9
5.3
6.8
8.7
11.2
5.6
7.1
4
Max
9.7
13.2
6.4
8.4
13.2
16.7
8.1
10.1
13.6
17.1
8.6
10.6
10
T
A
≤85_C
Typ
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
11.5
15.0
7.5
9.5
15.5
19.0
9.5
11.5
16.0
19.5
10.0
12.0
10
Typical @ 25_C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Note 7)
20
pF
7. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
¯
V
CC
¯
f
in
+ I
CC
. C
PD
is used to determine the no--load dynamic
power consumption: P
D
= C
PD
¯
V
CC2
¯
f
in
+ I
CC
¯
V
CC
.
-
-55_C
≤T
A
≤125_C
Typ
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max
11.5
15.0
7.5
9.5
15.5
19.0
9.5
11.5
16.0
19.5
10.0
12.0
10
pF
ns
ns
Unit
ns
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4
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