The AS7C3256 is a 3.3V high performance CMOS 262,144-bit Static Random-Access Memory (SRAM) organized as 32,768 words × 8 bits.
It is designed for memory applications requiring fast data access at low voltage, including Pentium
TM
, PowerPC
TM
, and portable computing.
Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins.
The device enters standby mode when CE is HIGH. CMOS standby mode consumes
≤3.6
mW (≤1.1 mW for the L version). Normal
operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Both versions of the AS7C3256 offer 2.0V data retention.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 3/3/4/5 ns are ideal for
high performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on
the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after
outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/
O pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C3256 is packaged in
high volume industry standard packages.
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND
Power dissipation
Storage temperature (plastic)
Temperature under bias
DC output current
Symbol
V
CC
V
IN
P
D
T
stg
T
bias
I
out
Min
–0.5
–0.5
–
–55
–10
–
Max
+4.6
+6.0
1.0
+150
+85
20
Unit
V
V
W
o
C
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.