Hitachi Single-Chip Microcomputer
H8S/2350
Series Overview
ADE-802-207
06/01/97
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the
whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the
characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no
responsibility for any intellectual property claims or other problems that may result from
applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.
Contents
Preface ....... .....................................................................................................1
Intended Readership .............................................................................................................. 1
Related Documents................................................................................................................ 1
Section 1 H8S/2350 Series Features ...............................................................3
1.1 H8S/2350 Series Functions .............................................................................................. 3
1.2 Pin Description ................................................................................................................ 7
Pin Arrangement.......................................................................................................... 7
Pin Functions............................................................................................................... 9
1.3 Block Diagram................................................................................................................. 11
Section 2 CPU................................................................................................13
2.1 Features ........................................................................................................................... 13
Feature 13
Differences between the H8S/2600 CPU and the H8S/2000 CPU................................. 14
Differences from H8/300 CPU..................................................................................... 14
Differences from H8/300H CPU .................................................................................. 15
2.2 Register Configuration ..................................................................................................... 16
CPU Internal Register Configuration ........................................................................... 16
General Registers ........................................................................................................ 17
Usage of General Registers.......................................................................................... 17
Control Registers......................................................................................................... 17
2.3 Data Formats.................................................................................................................... 20
General Register Data Formats .................................................................................... 21
Memory Data Formats................................................................................................. 21
2.4 Addressing Modes............................................................................................................ 23
Effective Address (EA) Calculation............................................................................. 23
2.5 Instruction Set.................................................................................................................. 25
Features....................................................................................................................... 25
Assembler Format ....................................................................................................... 25
Instruction Set Table.................................................................................................... 26
Number of States Required for Execution.................................................................... 40
2.6 Basic Bus Timing............................................................................................................. 42
Basic Clock Timing..................................................................................................... 42
CPU Read/Write Cycles .............................................................................................. 43
On-Chip Memory Access Cycle (One-State Access).................................................... 44
2.7 Processing States.............................................................................................................. 47
Reset State................................................................................................................... 47
Program Execution State ............................................................................................. 47
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Exception-Handling State............................................................................................ 47
Bus-Released State ...................................................................................................... 47
Power-Down State....................................................................................................... 47
State Transition Diagram............................................................................................. 48
2.8 Exception Handling ......................................................................................................... 49
Exception Handling Types and Priorities..................................................................... 49
Exception Handling Operation..................................................................................... 49
2.9 Interrupts ......................................................................................................................... 51
Interrupt Control.......................................................................................................... 51
Block Diagram of Interrupt Controller......................................................................... 51
Block Diagram of Interrupt Control Operation ............................................................ 52
Interrupt Control Mode 0............................................................................................. 53
Interrupt Control Mode 2............................................................................................. 53
2.10 Operating Modes............................................................................................................ 56
Normal Modes (Modes 1 to 3) ..................................................................................... 56
Advanced Modes (Modes 4 to 7) ................................................................................. 56
2.11 Address Map .................................................................................................................. 58
Address Map in Each Operating Mode ........................................................................ 58
Section 3 Peripheral Functions....................................................................... 61
3.1 Bus Controller (BSC)....................................................................................................... 61
3.1.1 Area Partitioning ................................................................................................ 63
3.1.2 Basic Bus Interface............................................................................................. 64
3.1.3 DRAM Interface ................................................................................................. 67
3.1.4 Burst ROM Interface .......................................................................................... 71
3.2 DMA Controller (DMAC)................................................................................................ 73
Features....................................................................................................................... 73
DMAC Block Diagram................................................................................................ 74
Transfer Modes ........................................................................................................... 74
3.2.1 Short Address Mode ........................................................................................... 76
3.2.2 Full Address Mode.............................................................................................. 79
3.3 Data Transfer Controller (DTC) ....................................................................................... 82
Features....................................................................................................................... 82
DTC Block Diagram.................................................................................................... 83
3.3.1 Data Transfer Operation ..................................................................................... 83
3.3.2 Transfer Modes................................................................................................... 88
3.4 16-Bit Timer Pulse Unit (TPU) ........................................................................................ 92
Features....................................................................................................................... 92
TPU Block Diagram .................................................................................................... 94
Interrupt Sources and Data Transfer Controller (DTC) and DMA Controller (DMAC)
Activation.................................................................................................................... 95
Operation .................................................................................................................... 96
Waveform Output by Compare-Match......................................................................... 96
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PWM Modes ............................................................................................................... 97
Input Capture Operation .............................................................................................. 98
Phase Counting Mode.................................................................................................. 99
Buffer Operation.......................................................................................................... 101
Cascading.................................................................................................................... 102
Synchronous Operation................................................................................................ 103
3.5 Programmable Pulse Generator (PPG).............................................................................. 104
Features....................................................................................................................... 104
PPG Block Diagram .................................................................................................... 105
Example of Four-Phase Complementary Non-Overlapping Output .............................. 105
3.6 Watchdog Timer .............................................................................................................. 107
Features....................................................................................................................... 107
Watchdog Timer Block Diagram ................................................................................. 108
Watchdog Timer Operation ......................................................................................... 109
Interval Timer Operation ............................................................................................. 110
3.7 Serial Communication Interface (SCI) ............................................................................. 111
Features....................................................................................................................... 111
SCI Block Diagram ..................................................................................................... 112
3.7.1 SCI Asynchronous Mode .................................................................................... 113
3.7.2 SCI Synchronous Communication....................................................................... 115
3.8 Smart Card Interface ........................................................................................................ 118
Features....................................................................................................................... 118
Smart Card Interface Block Diagram........................................................................... 119
Outline of Operation.................................................................................................... 119
Schematic Connection Diagram................................................................................... 120
Data Format................................................................................................................. 120
3.9 A/D Converter ................................................................................................................. 121
Features....................................................................................................................... 121
A/D Converter Block Diagram .................................................................................... 122
Input Channel Setting .................................................................................................. 122
Operation..................................................................................................................... 123
3.10 D/A Converter................................................................................................................ 124
Features....................................................................................................................... 124
Operation..................................................................................................................... 124
D/A Converter Block Diagram .................................................................................... 125
3.11 I/O Ports......................................................................................................................... 126
Port Functions in Each Operating Mode ...................................................................... 127
3.12 RAM.............................................................................................................................. 131
Block Diagram of RAM .............................................................................................. 131
3.13 ROM (H8S/2351)*......................................................................................................... 132
Block Diagram of ROM .............................................................................................. 132
PROM Programming (ZTAT™) .................................................................................. 132
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