RG82845PE/SL6Q3 datasheet, PDF

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RG82845PE/SL6Q3: DescriptionMemory Controller, CMOS, PBGA478; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，176 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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RG82845PE/SL6Q3 Overview

Memory Controller, CMOS, PBGA478

RG82845PE/SL6Q3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
package instruction	BGA, BGA478,37X37,40
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B478
Number of terminals	478
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA478,37X37,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.5 V
Certification status	Not Qualified
Maximum slew rate	2930 mA
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM

RG82845PE/SL6Q3 Preview

Intel

845GE/845PE Chipset

Datasheet

Intel

82845GE Graphics and Memory Controller Hub (GMCH) and

Intel

82845PE Memory Controller Hub (MCH)

October 2002

Document Number:

251924-001

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 845GE/845PE chipset may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed by Intel.

Implementations of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.

Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other

countries.

*Other names and brands may be claimed as the property of others.

Intel

82845GE/82845PE

Datasheet

Contents

Introduction

...........................................................................................................13

1.1

1.2

1.3

1.4

Terminology ...................................................................................................13

Related Documents .......................................................................................14

Intel

845GE / 845PE Chipset System Overview ..........................................15

Intel

82845GE GMCH / 82845PE MCH Overview .......................................17

1.4.1 Host Interface....................................................................................17

1.4.2 System Memory Interface .................................................................17

1.4.3 Hub Interface ....................................................................................17

1.4.4 Multiplexed AGP and Intel

DVO Port Interface ...............................18

1.4.5 Graphics Overview (Intel

82845GE only)........................................18

1.4.6 Display Interfaces (Intel

82845GE only) .........................................19

Host Interface Signals....................................................................................23

DDR SDRAM Interface ..................................................................................25

Hub Interface .................................................................................................26

AGP Interface Signals....................................................................................26

2.4.1 AGP Addressing Signals...................................................................26

2.4.2 AGP Flow Control Signals ................................................................27

2.4.3 AGP Status Signals ..........................................................................27

2.4.4 AGP Strobes .....................................................................................28

2.4.5 PCI Signals–AGP Semantics............................................................29

2.4.6 PCI Pins during PCI Transactions on AGP Interface ........................30

Multiplexed DVO Device Signal Interfaces (Intel

82845GE only) ................30

2.5.1 Intel

DVO Signal Name to AGP Signal Name Pin

Mapping (Intel

82845GE only) ........................................................32

Analog Display (Intel

82845GE only) ...........................................................33

Clocks, Reset, and Miscellaneous Signals ....................................................34

RCOMP, VREF, VSWING Signals.................................................................34

Power and Ground Signals ............................................................................35

Functional Straps ...........................................................................................36

Intel

(G)MCH Sequencing Requirements ....................................................36

Reset States ..................................................................................................37

2.12.1 Full and Warm Reset States .............................................................37

Platform Configuration ...................................................................................40

Routing Configuration Accesses....................................................................41

3.3.1 Standard PCI Bus Configuration Mechanism ...................................42

3.3.2 PCI Bus #0 Configuration Mechanism ..............................................42

3.3.3 Primary PCI and Downstream Configuration Mechanism.................42

3.3.4 AGP/PCI_B Bus Configuration Mechanism ......................................42

I/O Mapped Registers ....................................................................................44

3.4.1 CONFIG_ADDRESS—Configuration Address Register ...................44

3.4.2 CONFIG_DATA—Configuration Data Register ................................45

Intel

(G)MCH Internal Device Registers ......................................................46

3.5.1 DRAM Controller/Host-Hub Interface Device Registers (Device 0) ..46

Signal Description

..............................................................................................21

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

..........................................................................................39

3.1

3.2

3.3

3.4

3.5

Intel

82845GE/82845PE

Datasheet

3.5.2

VID—Vendor Identification Register (Device 0) ................ 48

DID—Device Identification Register (Device 0)................. 48

PCICMD—PCI Command Register (Device 0) ................. 49

PCISTS—PCI Status Register (Device 0) ......................... 50

RID—Revision Identification Register (Device 0) .............. 51

SUBC—Sub-Class Code Register (Device 0) ................... 51

BCC—Base Class Code Register (Device 0).................... 51

MLT—Master Latency Timer Register (Device 0) ............. 52

HDR—Header Type Register (Device 0) .......................... 52

APBASE—Aperture Base Configuration

3.5.1.11 SVID—Subsystem Vendor Identification

3.5.1.12 SID—Subsystem Identification Register (Device 0) .......... 54

3.5.1.13 CAPPTR—Capabilities Pointer Register (Device 0) ......... 54

3.5.1.14 AGPM—AGP Miscellaneous Configuration

3.5.1.15 GC—Graphics Control Register (Device 0)

(Intel

82845GE only) ....................................................... 56

3.5.1.16 DRB[0:3]—DRAM Row Boundary Register (Device 0) ..... 58

3.5.1.17 DRA—DRAM Row Attribute Register (Device 0) .............. 59

3.5.1.18 DRT—DRAM Timing Register (Device 0) ......................... 60

3.5.1.19 DRC—DRAM Controller Mode Register (Device 0) .......... 61

3.5.1.20 PAM[0:6]—Programmable Attribute Map Registers

(Device 0) .......................................................................... 62

3.5.1.21 FDHC—Fixed SDRAM Hole Control Register (Device 0) . 65

3.5.1.22 SMRAM—System Management RAM Control

3.5.1.23 ESMRAMC—Extended System Management RAM

Control Register (Device 0) ............................................... 66

3.5.1.24 ACAPID—AGP Capability Identifier Register (Device 0) .. 67

3.5.1.25 AGPSTAT—AGP Status Register (Device 0) ................... 67

3.5.1.26 AGPCMD—AGP Command Register (Device 0) .............. 68

3.5.1.27 AGPCTRL—AGP Control Register (Device 0) .................. 68

3.5.1.28 APSIZE—Aperture Size Register (Device 0) .................... 69

3.5.1.29 ATTBASE—Aperture Translation Table Register

(Device 0) .......................................................................... 69

3.5.1.30 AMTT—AGP MTT Control Register (Device 0)................. 70

3.5.1.31 LPTT—AGP Low Priority Transaction Timer

3.5.1.32 GMCHCFG—GMCH/MCH Configuration

3.5.1.33 ERRSTS—Error Status Register (Device 0) ..................... 72

3.5.1.34 ERRCMD—Error Command Register (Device 0).............. 73

3.5.1.35 SMICMD—SMI Command Register (Device 0) ................ 74

3.5.1.36 SCICMD—SCI Command Register (Device 0) ................. 74

3.5.1.37 SKPD—Scratchpad Data Register (Device 0) .................. 74

3.5.1.38 CAPREG—Capability Identification Register (Device 0) ... 74

Host-to-AGP Bridge Registers (Device 1)......................................... 75

3.5.2.1 VID1—Vendor Identification Register (Device 1) .............. 76

3.5.2.2 DID1—Device Identification Register (Device 1)............... 76

3.5.2.3 PCICMD1—PCI Command Register (Device 1) ............... 77

3.5.2.4 PCISTS1—PCI Status Register (Device 1)....................... 78

3.5.2.5 RID1—Revision Identification Register (Device 1) ............ 78

3.5.2.6 SUBC1—Sub-Class Code Register (Device 1) ................. 79

3.5.2.7 BCC1—Base Class Code Register (Device 1).................. 79

3.5.1.1

3.5.1.2

3.5.1.3

3.5.1.4

3.5.1.5

3.5.1.6

3.5.1.7

3.5.1.8

3.5.1.9

3.5.1.10

Intel

82845GE/82845PE

Datasheet

3.5.3

3.5.4

MLT1—Master Latency Timer Register (Device 1) ...........79

HDR1—Header Type Register (Device 1).........................80

PBUSN1—Primary Bus Number Register (Device 1) .......80

SBUSN1—Secondary Bus Number Register (Device 1)...80

SUBUSN1—Subordinate Bus Number Register

(Device 1) ..........................................................................81

3.5.2.13 SMLT1—Secondary Bus Master Latency Timer

3.5.2.14 IOBASE1—I/O Base Address Register (Device 1)............82

3.5.2.15 IOLIMIT1—I/O Limit Address Register (Device 1).............82

3.5.2.16 SSTS1—Secondary Status Register (Device 1) ...............83

3.5.2.17 MBASE1—Memory Base Address Register (Device 1) ....84

3.5.2.18 MLIMIT1—Memory Limit Address Register (Device 1) .....84

3.5.2.19 PMBASE1—Prefetchable Memory Base Address

3.5.2.20 PMLIMIT1—Prefetchable Memory Limit Address

3.5.2.21 BCTRL1—Bridge Control Register (Device 1) ..................86

3.5.2.22 ERRCMD1—Error Command Register (Device 1)............87

Integrated Graphics Device Registers (Device 2)

(Intel

82845GE only) .......................................................................88

3.5.3.1 VID2—Vendor Identification Register (Device 2) ..............89

3.5.3.2 DID2—Device Identification Register (Device 2)...............89

3.5.3.3 PCICMD2—PCI Command Register (Device 2) ...............90

3.5.3.4 PCISTS2—PCI Status Register (Device 2) .......................91

3.5.3.5 RID2—Revision Identification Register (Device 2) ............91

3.5.3.6 CC—Class Code Register (Device 2) ...............................92

3.5.3.7 CLS—Cache Line Size Register (Device 2) ......................92

3.5.3.8 MLT2—Master Latency Timer Register (Device 2) ...........92

3.5.3.9 HDR2—Header Type Register (Device 2).........................93

3.5.3.10 GMADR —Graphics Memory Range Address

3.5.3.11 MMADR—Memory Mapped Range Address

3.5.3.12 SVID2—Subsystem Vendor Identification

3.5.3.13 SID2—Subsystem Identification Register (Device 2) ........94

3.5.3.14 ROMADR—Video BIOS ROM Base Address

Registers (Device 2) ..........................................................95

3.5.3.15 CAPPOINT—Capabilities Pointer Register (Device 2)......95

3.5.3.16 INTRLINE—Interrupt Line Register (Device 2)..................95

3.5.3.17 INTRPIN—Interrupt Pin Register (Device 2) .....................96

3.5.3.18 MINGNT—Minimum Grant Register (Device 2) ................96

3.5.3.19 MAXLAT—Maximum Latency Register (Device 2)............96

3.5.3.20 PMCAPID—Power Management Capabilities ID

3.5.3.21 PMCAP—Power Management Capabilities

3.5.3.22 PMCS—Power Management Control/Status

Device 6 Registers ............................................................................98

3.5.4.1 DWTC—DRAM Write Throttling Control

3.5.4.2 DRTC—DRAM Read Throttling Control

3.5.2.8

3.5.2.9

3.5.2.10

3.5.2.11

3.5.2.12

Intel

82845GE/82845PE

Datasheet

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RG82845PE/SL6Q3 Related Products

	RG82845PE/SL6Q3	RG82845PE/SL6H5	RG82845GE/SL6PS
Description	Memory Controller, CMOS, PBGA478	Memory Controller, CMOS, PBGA478	Memory Controller, CMOS, PBGA478
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Intel	Intel	Intel
package instruction	BGA, BGA478,37X37,40	BGA, BGA478,37X37,40	BGA, BGA478,37X37,40
Reach Compliance Code	compliant	compliant	compliant
JESD-30 code	S-PBGA-B478	S-PBGA-B478	S-PBGA-B478
Number of terminals	478	478	478
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA
Encapsulate equivalent code	BGA478,37X37,40	BGA478,37X37,40	BGA478,37X37,40
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
power supply	1.5 V	1.5 V	1.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum slew rate	2930 mA	2930 mA	2930 mA
Nominal supply voltage	1.5 V	1.5 V	1.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM

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